R5F5651EDDFM datasheet(93/188 Pages) RENESAS

93 / 188 page

R01DS0276EJ0240 Rev.2.40

Page 93 of 188

Oct 31, 2023

RX65N Group, RX651 Group

2. Electrical Characteristics

Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled.

Note 2. Peripheral module clocks are supplied.

Note 3. ICC depends on the f (ICLK) as follows (when ICLK/PCLKA : PCLKB/PCLKC/PCLKD : BCLK : BCLK pin = 2 : 1 : 2 : 1 and

EXTAL = 12 MHz).

 D version

ICC max = 0.28 × f + 6.5 (full operation in high-speed operating mode)

ICC typ = 0.16 × f + 2.8 (normal operation in high-speed operating mode)

ICC typ = 0.1 × f + 1.0 (ICLK 1 MHz max) (low-speed operating mode 1)

ICC max = 0.15 × f + 6.5 (sleep mode)

 G version

ICC max = 0.30 × f + 9.0 (full operation in high-speed operating mode)

ICC typ = 0.16 × f + 2.8 (normal operation in high-speed operating mode)

ICC typ = 0.1 × f + 1.0 (ICLK 1 MHz max) (low-speed operating mode 1)

ICC max = 0.16 × f + 9.0 (sleep mode)

Note 4. Whether the peripheral module clocks are supplied or stopped is controlled only by the bit settings in the module stop control

Table 2.6

DC Characteristics (3) (Products with 1 Mbyte of code flash memory or less)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

Ta = Topr

Item

Symbol

D version

G version

Unit

Test Conditions

Typ.

Max.

Typ.

Max.

Supply

current*1

Full operation*2

ICC*3

—

ICLK = 120 MHz,

PCLKA = 120 MHz,

PCLKB = 60 MHz,

PCLKC = 60 MHz,

PCLKD = 60 MHz,

FCLK = 60 MHz,

BCLK = 120 MHz,

BCLK pin = 60 MHz

Normal

operation

Peripheral module clocks are supplied

—

Peripheral module clocks are stopped

*4, *5

—

Core

Mark

Peripheral module clocks are stopped

*4, *5

—

Sleep mode: Peripheral module clocks are

supplied*4

All module clock stop mode (reference value)

Low-speed operating mode 1: Peripheral module

clocks are stopped*4

1.1

—

1.1

—

All clocks 1 MHz

Low-speed operating mode 2: Peripheral module

clocks are stopped*4

1.1

—

1.1

—

All clocks 32.768

kHz

Software standby mode

1.6

6.4

1.6

9.8

Power is supplied to the standby RAM and USB

resume detecting unit (USB0 only)

15.5

µA

Power is not

supplied to the

standby RAM and

USB resume

detecting unit

(USB0 only)

Low power consumption

function of the power-on

reset circuit is disabled*6

11.5

Low power consumption

function of the power-on

reset circuit is enabled*7

4.9

Increase current

by operating RTC

When a low CL crystal is in

use

1—

—

When a standard CL crystal

is in use

2—

—

When the RTC is

operating while VCC is

not supplied (Only the

RTC and sub-clock

oscillator operate with

the battery backup

function)

When a low CL crystal is in

use

0.9

—

0.9

—

VBATT = 2.0 V,

VCC = 0 V

1.6

—

1.6

—

VBATT = 3.3 V,

VCC = 0 V

When a standard CL crystal

is in use

1.6

—

1.6

—

VBATT = 1.62 V,

VCC = 0 V

1.7

—

1.7

—

VBATT = 2.0 V,

VCC = 0 V

3.3

—

3.3

—

VBATT = 3.3 V,

VCC = 0 V

Inrush current on

release from deep

software standby mode

Inrush current*8

IRUSH

—70

—

Total inrush current*8

ERUSH

—

1.0

—

1.0

µC

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