R5F5651EDDFM datasheet(144/188 Pages) RENESAS

144 / 188 page

R01DS0276EJ0240 Rev.2.40

Page 144 of 188

Oct 31, 2023

RX65N Group, RX651 Group

2. Electrical Characteristics

2.4.7.11

QSPI

Note 1. tPBcyc: PCLKB cycle

Note 2. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in

combination with the pins in the same group. All QSPI AC timings are measured in combination with the pins in the same group.

Note 3. In the G-version products, the AC characteristics are measured by setting the drive capacity control register 2 corresponding the

QSPCLK pin as a high-speed interface high-drive output.

Figure 2.61

QSPI Clock Timing

Figure 2.62

Transmit/Receive Timing (CPHA = 0)

Table 2.39

QSPI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.*3

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions*2

QSPI

QSPCLK clock cycle

tQScyc

4080

tPBcyc

Figure 2.61

Data input setup time

tSu

6.5

—

Figure 2.62,

Figure 2.63

Data input hold time

tIH

5—

SS setup time

tLEAD

1.5

8.5

tQScyc

SS hold time

tLAG

tQScyc

Data output delay time

tOD

—

10.0

Data output hold time

tOH

–5

—

Successive transmission delay time

tTD

tQScyc

QSPCLK

output

MSB IN

MSB OUT

LSB OUT

IDLE

DATA

LSB IN

DATA

QSSL

output

QSPCLK

CPOL = 0

output

QSPCLK

CPOL = 1

output

QMI,

QIO0 to QIO3

input

QMO,

QIO0 to QIO3

output

tLEAD

tLAG

tSU

tIH

tOH

tOD

tTD

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