9.5 Layout

9.5.1 Layout Guidelines

A proper layout is critical for the operation of any switched mode power supply, especially at high switching

frequencies. Therefore, the PCB layout of the TPSM8281x demands careful attention to make sure of best

performance. A poor layout can lead to issues like bad line and load regulation, instability, increased EMI

radiation, and noise sensitivity. Refer to the Five Steps to a Great PCB Layout for a Step-Down Converter analog

design journal for a detailed discussion of general best practices. Specific recommendations for the device are

listed below.

• The input capacitor must be placed as close as possible to the VIN and GND pins of the device. This is the

most critical component placement. Route the input capacitor directly to the VIN and GND pins avoiding vias.

• Place the output capacitor ground close to the VOUT and GND pins and route directly avoiding vias.

• Place the FB resistors, R1 and R2, and the feedforward capacitor CFF close to the FB pin and place CSS

close to the SS/TR pin to minimize noise pickup.

• Place the RCF resistor close to the COMP/FSET pin to minimize the parasitic capacitance.

• The recommended layout is implemented on the EVM and shown in the EVM User's Guide and in Section

9.5.2.

• The recommended land pattern for the TPSM8281x is shown at the end of this data sheet. For best

manufacturing results, create the pads as solder mask defined (SMD), when some pins (such as VIN, VOUT,

and GND) are connected to large copper planes. Using SMD pads keeps each pad the same size and avoids

solder pulling the device during reflow.

9.5.2 Layout Examples

The example below shows a cut-out from the layout of the MagPack evaluation module. To further reduce EMI,

current loops are kept small and noisy traces kept short.

GND

VIN

GND

C

IN

C

OUT

C

SS

R

CF

C

FF

R

1

U1

SW

GND

VIN

VOUT

Figure 9-38. Example Layout VCA Package

The same rules also apply to the layout with the SIL package. The pin-outs of both the SIL and the VCA package

are optimized for short connections between the device and input or output capacitors. The copper keepout (only

for the SIL package) is for top copper layer only. Other PCBs layers can enter this keepout.

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TPSM82810, TPSM82813

SLUSDN6D – SEPTEMBER 2019 – REVISED JUNE 2026

Copyright © 2026 Texas Instruments Incorporated

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