R7KA8M2AFECAC datasheet(185/295 Pages) RENESAS

185 / 295 page

Table 2.65

IIC timing (1) (2 of 2)

Conditions:

1. Middle drive output is selected when VCC is 2.70 V or above, High drive output is selected when VCC is 1.62 to 1.95 V in the port drive

capability bit in the PmnPFS register for the following pins: SDA0_B, SCL0_B, SDA1_B, SCL1_B, SDA2_B, SCL2_B

2. The following pins do not require setting: SCL0_A, SDA0_A. SCL1_A, SDA1_A. SCL2_A, SDA2_A

3. Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership.

For the IIC interface, the AC portion of the electrical characteristics is measured for each group.

Parameter

Symbol

VCC

Min

Max

Unit

Test

conditions

IIC

(Fast mode)

ICFER.FMPE = 0

SCL input cycle time

tSCL

2.70 V or above

6 (12) × tIICcyc + 600

—

Figure 2.88

1.62 to 1.95 V

SCL input high pulse

width

tSCLH

2.70 V or above

3 (6) × tIICcyc + 300

—

1.62 to 1.95 V

SCL input low pulse

width

tSCLL

2.70 V or above

3 (6) × tIICcyc + 300

—

1.62 to 1.95 V

SCL, SDA rise time

tSr

2.70 V or above

300

1.62 to 1.95 V

SCL, SDA fall time

tSf

2.70 V or above

20 × (external pullup

voltage/5.5 V)*1

300

1.62 to 1.95 V

SCL, SDA input spike

pulse removal time

tSP

2.70 V or above

1 (4) × tIICcyc ns

1.62 to 1.95 V

SDA input bus free time

when wakeup function is

disabled

tBUF

2.70 V or above

3 (6) × tIICcyc + 300

—

1.62 to 1.95 V

SDA input bus free time

when wakeup function is

enabled

tBUF

2.70 V or above

3 (6) × tIICcyc + 4 ×

tPcyc + 300

—

1.62 to 1.95 V

START condition input

hold time when wakeup

function is disabled

tSTAH

2.70 V or above

tIICcyc + 300

—

1.62 to 1.95 V

START condition input

hold time when wakeup

function is enabled

tSTAH

2.70 V or above

1 (5) × tIICcyc + tPcyc

+ 300

—

1.62 to 1.95 V

Repeated START

condition input setup time

tSTAS

2.70 V or above

300

—

1.62 to 1.95 V

STOP condition input

setup time

tSTOS

2.70 V or above

300

—

1.62 to 1.95 V

Data input setup time

tSDAS

2.70 V or above

tIICcyc + 50

—

1.62 to 1.95 V

Data input hold time

tSDAH

2.70 V or above

—

1.62 to 1.95 V

SCL, SDA capacitive

load

2.70 V or above

—

400

1.62 to 1.95 V

Note:

tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.

Note:

Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.

Note:

Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the IIC

interface, the AC portion of the electrical characteristics is measured for each group.

Note 1. Only supported for SCL0_A, SDA0_A, SCL1_A, SDA1_A, SCL2_A, and SDA2_A.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 185 of 295

R7KA8M2AFECAC bảng dữ liệu(PDF) 185 Page - Renesas Technology Corp

R7KA8M2AFECAC bảng dữ liệu(HTML) 185 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL