R7KA8M2AFECAC datasheet(186/295 Pages) RENESAS

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Table 2.66

IIC timing (2)

Setting of the SCL0_A, SDA0_A, SCL1_A, SDA1_A. SCL2_A, SDA2_A pins are not required with the port drive capability bit in the PmnPFS

Parameter

Symbol

VCC

Min

Max

Unit

Test

conditions

IIC

(Fast-mode+)

ICFER.FMPE = 1

SCL input cycle time

tSCL

2.70 V or

above

6 (12) × tIICcyc +

240

—

Figure 2.88

1.62 to 1.95V

SCL input high pulse

width

tSCLH

2.70 V or

above

3 (6) × tIICcyc + 120 —

1.62 to 1.95V

SCL input low pulse width tSCLL

2.70 V or

above

3 (6) × tIICcyc + 120 —

1.62 to 1.95V

SCL, SDA rise time

tSr

2.70 V or

above

—

120

1.62 to 1.95V

SCL, SDA fall time

tSf

2.70 V or

above

20 × (external

pullup voltage/

5.5V)

120

1.62 to 1.95V

SCL, SDA input spike

pulse removal time

tSP

2.70 V or

above

1 (4) × tIICcyc

1.62 to 1.95V

SDA input bus free time

when wakeup function is

disabled

tBUF

2.70 V or

above

3 (6) × tIICcyc + 120 —

1.62 to 1.95V

SDA input bus free time

when wakeup function is

enabled

tBUF

2.70 V or

above

3 (6) × tIICcyc + 4 ×

tPcyc + 120

—

1.62 to 1.95V

Start condition input

hold time when wakeup

function is disabled

tSTAH

2.70 V or

above

tIICcyc + 120

—

1.62 to 1.95V

START condition input

hold time when wakeup

function is enabled

tSTAH

2.70 V or

above

1 (5) × tIICcyc +

tPcyc + 120

—

1.62 to 1.95V

Restart condition input

setup time

tSTAS

2.70 V or

above

120

—

1.62 to 1.95V

Stop condition input setup

time

tSTOS

2.70 V or

above

120

—

1.62 to 1.95V

Data input setup time

tSDAS

2.70 V or

above

tIICcyc + 30

—

1.62 to 1.95V

Data input hold time

tSDAH

2.70 V or

above

—

1.62 to 1.95V

SCL, SDA capacitive load Cb*1

2.70 V or

above

—

550

1.62 to 1.95V

Note:

tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 186 of 295

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