R7KA8M2AFECAC datasheet(68/295 Pages) RENESAS

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Table 2.20

Current of high-speed mode, maximum data processing (MVE operation), CPU0 active, CPU1 Deep

Sleep, peripheral clock OFF (DCDC mode)

Parameter

Symbol

Typ

Max

Unit

Test conditions

95 °C

105 °C

125 °C

Supply

current

*1*2

CPUCLK0 = 1

GHz

CPUCLK1 = 250

MHz

VSCR_1

ICC_DCDC*4

115

308

—

VCC_DCDC = 3.3 V

CPU1 = Deep Sleep

IDD*3

295

792

—

CPUCLK0 = 800

MHz

CPUCLK1 = 200

MHz

VSCR_1

ICC_DCDC*4

—

317

—

IDD*3

244

—

813

—

CPUCLK0 = 600

MHz

CPUCLK1 = 200

MHz

VSCR_1

ICC_DCDC*4

—

348

IDD*3

194

—

895

CPUCLK0 = 600

MHz

CPUCLK1 = 150

MHz

VSCR_2

ICC_DCDC*4

251

285

331

IDD*3

187

658

746

868

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

Note 3. IDD depends on f (CPUCLK0 and ICLK) as follows.

IDD Typ. = 0.25 × fCPUCLK0 + 0.13 × fICLK + 21 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 95℃) = 0.27 × fCPUCLK0 + 0.13 × fICLK + 474 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 105℃) = 0.27 × fCPUCLK0 + 0.13 × fICLK + 549 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 125℃) = 0.27 × fCPUCLK0 + 0.13 × fICLK + 704 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 95℃) = 0.27 × fCPUCLK0 + 0.14 × fICLK + 461 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 105℃) = 0.27 × fCPUCLK0 + 0.14 × fICLK + 533 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 125℃) = 0.27 × fCPUCLK0 + 0.14 × fICLK + 686 (unit : mA, fCPUCLK0 and fICLK are MHz)

Note 4. Typical DCDC efficiency and the voltage of the test conditions are applied.

Note 5. Same frequency condition is applied as in the maximum condition.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

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