R7KA8M2AFECAC datasheet(181/295 Pages) RENESAS

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Table 2.64

OSPI timing (9 of 9)

Conditions:

High-speed high drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: OM_n_SCLK,

OM_n_SCLKN, OM_n_SIO7-0, OM_n_DQS.

Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: OM_n_CS0, OM_n_CS1.

Load capacitance C = 15pF

Item

Symbol

VCC/VCC2 VDD

Min

Max

Unit

Note

Clock High to DQS input*4

tCKHDSH

2.70 V or

above

VSCR_1,

voltage

range 1

—

tPERIOD × (1 +

DDRSMPEX

[3:0]) − 8.5

Figure 2.85

VSCR_2,

voltage

range 2

1.62 V to

2.00 V

VSCR_1,

voltage

range 1

—

tPERIOD × (1 +

DDRSMPEX

[3:0]) − 12.5

VSCR_2,

voltage

range 2

Note:

n = 0, 1

Note 1. This restriction does not need to be met when using the JESD251 Profile 1.0 memory with an external pull-down attached to the

OM_DQS pin.

Note 2. Condition: COMCFG.OEASTEX = 1

Note 3. Condition: LIOCFGCSx.CSASTEX = 1

Note 4. See the datasheet of memory and set DDRSMPEX[3:0] bits to satisfy this value.

tPERIOD

tCKDCD

tDSDCD

tPERIOD

Differential

OM_SCLK output

tCKMPW

tCKDCD

Single end

OM_SCLK output

OM_DQS input

VOX (min)

70%

30%

70%

tSRck

70%

30%

70%

tSRck

70%

30%

70%

tSU

OM_SIOn input

(relative to

OM_SCLK or

OM_DQS)

OM_SIOn output

(relative to

OM_SCLK)

tOV

tOH

tSR

tCKMPW

tDSMPW

VOX (max)

VOL (30%)

VOH (70%)

VIL (30%)

VIH (70%)

tSU

tSR

tSRck

tCKMPW

tDSMPW

Figure 2.83

OSPI clock / DS timing

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 181 of 295

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