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TMS320DM641 bảng dữ liệu(PDF) 92 Page - Texas Instruments |
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TMS320DM641 bảng dữ liệu(HTML) 92 Page - Texas Instruments |
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92 / 179 page  Enhanced Direct Memory Access (EDMA) Controller 92 June 2003 − Revised October 2005 SPRS222E Table 4−3. TMS320DM641/DM640 EDMA Channel Synchronization Events† (Continued) EDMA CHANNEL EVENT DESCRIPTION EVENT NAME 57 VP1EVTUA VP1 Channel A Cb event DMA request [For DM641 Only; “None” for DM640] 58 VP1EVTVA VP1 Channel A Cr event DMA request [For DM641 Only; “None” for DM640] 59−63 – None † In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234). 4.4.2 EDMA Peripheral Register Description(s) Table 4−4. EDMA Registers (C64x) HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A0 0800 − 01A0 FF98 − Reserved 01A0 FF9C EPRH Event polarity high register 01A0 FFA4 CIPRH Channel interrupt pending high register 01A0 FFA8 CIERH Channel interrupt enable high register 01A0 FFAC CCERH Channel chain enable high register 01A0 FFB0 ERH Event high register 01A0 FFB4 EERH Event enable high register 01A0 FFB8 ECRH Event clear high register 01A0 FFBC ESRH Event set high register 01A0 FFC0 PQAR0 Priority queue allocation register 0 01A0 FFC4 PQAR1 Priority queue allocation register 1 01A0 FFC8 PQAR2 Priority queue allocation register 2 01A0 FFCC PQAR3 Priority queue allocation register 3 01A0 FFDC EPRL Event polarity low register 01A0 FFE0 PQSR Priority queue status register 01A0 FFE4 CIPRL Channel interrupt pending low register 01A0 FFE8 CIERL Channel interrupt enable low register 01A0 FFEC CCERL Channel chain enable low register 01A0 FFF0 ERL Event low register 01A0 FFF4 EERL Event enable low register 01A0 FFF8 ECRL Event clear low register 01A0 FFFC ESRL Event set low register 01A1 0000 − 01A3 FFFF – Reserved |
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