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STM32F103XC bảng dữ liệu(PDF) 91 Page - STMicroelectronics |
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STM32F103XC bảng dữ liệu(HTML) 91 Page - STMicroelectronics |
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91 / 118 page ![]() STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 91/118 I2S - SPI characteristics Unless otherwise specified, the parameters given in Table 51 for SPI or in Table 52 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 51. SPI characteristics(1) (2) Symbol Parameter Conditions Min Max Unit fSCK 1/tc(SCK) SPI clock frequency Master mode 0 18 MHz Slave mode 0 18 tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF 8 ns tsu(NSS) (3) NSS setup time Slave mode tC(SCK) th(NSS) (3) NSS hold time Slave mode 0.5tC(SCK) tw(SCKH) (3) tw(SCKL) (3) SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 50 60 tsu(MI) (3) tsu(SI) (3) Data input setup time Master mode 10 Slave mode 5 th(MI) (3) th(SI) (3) Data input hold time Master mode, fPCLK = 36 MHz, presc = 4 15 Slave mode, fPCLK = 36 MHz, presc = 4 5 Master mode, fPCLK = TBD TBD(4) Slave mode, fPCLK = TBD TBD(4) ta(SO) (3)(5) Data output access time Slave mode, fPCLK = 36 MHz, presc = 4 0 60 Slave mode, fPCLK = TBD 0 TBD tdis(SO) (3)(6) Data output disable time Slave mode 5 TBD tv(SO) (3)(1) Data output valid time Slave mode (after enable edge), fPCLK = 36 MHz, presc = 4 30 fPCLK = TBD TBD tv(MO) (3)(1) Data output valid time Master mode (after enable edge), fPCLK = 36 MHz, presc = 4 10 fPCLK = TBD TBD TBD th(SO) (3) Data output hold time Slave mode (after enable edge) 30 th(MO) (3) Master mode (after enable edge) 10 1. TBD = to be determined. 2. Remapped SPI1 characteristics to be determined. 3. Values based on design simulation and/or characterization results, and not tested in production. 4. Depends on fPCLK. For example, if fPCLK= 8MHz, then tPCLK = 1/fPLCLK =125 ns and tv(MO) = 255 ns. 5. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 6. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z |
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