DIO1413/1414

Version 1.2, Sep 2024

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By keeping the SMBus data line high after the 8th data bit has been sent, the host will NACK (not acknowledge)

the final data byte that has been received from the client.

11.1.4. SMBus timeout

SMBus timeout function is supported by the DIO1413/1414. The device resets its SMBus protocol if the clock

line is maintained low for more than 30 ms. Setting the TIMEOUT bit in the consecutive ALERT register (see

section 12.11) will enable this function.

11.1.5. SMBus and I2C compatibility

SMBus and I2C are both supported by the DIO1413/1414. Here shows the key differences between SMBus and

I2C devices.

The DIO1413/1414 support I2C fast mode at 400 kHz, covering 100 kHz (maximum SMBus time).

(1) 10 kHz is the minimum frequency for SMBus communications.

(2) The condition of resetting the SMBus client protocol is that the clock is kept at a logic “0” for longer than 30

ms. The timeout functionality is disabled by default while it is enabled by writing to the bit 7 in the consecutive

ALERT register (TIMEOUT bit). I2C doesn’t have a timeout.

(3) I2C devices can’t support the ALERT response address functionality and it’s optional for SMBus.

The DIO1413/1414 SMBus interface will not respond to signals sent with an invalid slave address or an invalid

protocol, and the register contents will remain unaffected. Stretching of the SMCLK signal is supported if the

timing is managed by other SMBus components.

11.2. SMBus protocol

The DIO1413/1414 support various kind of byte protocols: Send bite, Read byte, Write byte, Receive byte and

Alert response address as valid protocols.

(1) Write byte: Writing one byte of data to the registers.

(2) Read byte: Reading one byte of data from the registers.

(3) Send byte: Setting the internal address register pointer to the correct address location. Noted that no data is

transferred during the Send byte protocol.

(4) Receive byte: Reading data from a register when the internal register address pointer is at the correct

location via Send byte. This is used for consecutive reads of the same register.

(5) Alert response address: the

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ALERT pin output can be interpreted as interrupt or as an SMBus Alert by the

host. When the

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ALERT pin is asserted, the host will send the Alert Response Address (ARA) to the general

address of 0001_100xb. The DIO1413/1414 will respond to the ARA in two steps: send the slave address of

DIO1413 or DIO1414. Then the channel mask bit will be set and the

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ALERT pin will be deasserted.