FN8389 datasheet(40/56 Pages) RENESAS

40 / 56 page

ISL28023

FN8389 Rev.6.03

Page 40 of 55

Oct 27, 2022

of the control bits within the Force Feedthrough Alert register is

defined in Table 35.

A2POL D[3], A2POL D[2]

The AxPOL bits control the polarity of an interrupt. A2POL bit

defines the SMBALERT2 pin active interrupt state. A1POL bit

defines the SMBALERT1 pin active interrupt state. Table 36

defines the functionality of the bit.

FORCEA2 D[1], FORCEA1 D[0]

The FORCEAx bits allow the user to force an interrupt by setting

the bit. FORCEA2 bit controls the SMBALERT2 pin state.

FORCEA1 bit controls the SMBALERT1 pin state. Table 37 defines

the functionality of the bit.

0X03 CLEAR FAULTS (S)

The Clear Faults register is a send byte command that clears all

faults pertaining to the status registers. Upon execution of the

command, the status registers return to the default state defined

in Table 2 on page 28.

0X7A STATUS VOUT (R/W)

The Status VOUT register is a read/writable byte register that

reports over and undervoltage warnings for the VBUS input.

VOUT OV WARNING D[6]

The VOUT OV Warning bit is set to 1 when an overvoltage fault

occurs on the VBUS input. The VBUS overvoltage threshold is set

from the VOUT OV Threshold Set register. In the event of a VBUS

overvoltage condition, the VOUT OV Warning is latched to 1.

Writing a 1 to the VOUT OV Warning bit will clear the warning

resulting in a bit value equal to 0.

VOUT UV WARNING D[5]

The VOUT UV Warning bit is set to 1 when an undervoltage fault

occurs on the VBUS input. The VBUS undervoltage threshold is set

from the VOUT UV Threshold Set register. In the event of a VBUS

undervoltage condition, the VOUT UV Warning is latched to 1.

Writing a 1 to the VOUT UV Warning bit will clear the warning

resulting in a bit value equal to 0.

0X7B STATUS IOUT (R/W)

The Status IOUT register is a read/writable byte register that

reports an overcurrent warning for the VSHUNT input.

IOUT OC WARNING D[5]

The IOUT OC Warning bit is set to 1 when an overcurrent fault

occurs on the VSHUNT input. The VSHUNT overcurrent threshold is

set from the IOUT OC Threshold Set register. In the event of a

VSHUNT overcurrent condition, the IOUT OC Warning is latched

to 1. Writing a 1 to the IOUT OC Warning bit will clear the warning

resulting in a bit value equal to 0.

0X7D STATUS TEMPERATURE (R/W)

The Status Temperature register is a read/writable byte register

that reports an over-temperature warning initiated from the

internal temperature sensor.

OT WARNING D[6]

The OT Warning bit is set to 1 when an over-temperature fault

occurs from the internal temperature sensor. The

over-temperature threshold is set from the VOUT OV Threshold

Set register. In the event of an over-temperature condition, the OT

Warning bit is latched to 1. Writing a 1 to the OT Warning bit will

clear the warning resulting in a bit value equal to 0.

0X7E STATUS CML (R/W)

The Status CML register is a read/writable byte register that

reports warnings and errors associated with communications,

logic and memory.

TABLE 35. 0xDE FORCE FEEDTHROUGH ALERT REGISTER DEFINITION

BIT

NUMBER

D[7:4]

D[3]

D[2]

D[1]

D[0]

Bit Name

N/A

A2POL

A1POL

FORCE A2 FORCE A1

Default

Value

0000

TABLE 36. AxPol BIT DEFINED

A2POL D[3], A1POL D[2]

INTERRUPT

ACTIVE STATE

Low

1High

TABLE 37. FORCEAx BIT DEFINED

FORCEA2 D[1], FORCEA1 D[0]

INTERRUPT STATUS

Normal

Interrupt Forced

TABLE 38. 0x7A STATUS VOUT REGISTER DEFINITION

BIT NUMBER

D[7]

D[6]

D[5]

D[4:0]

Bit Name

N/A

VOUT OV

Warning

VOUT UV

Warning

N/A

Default

Value

0 0000

TABLE 39. 0x7B STATUS IOUT REGISTER DEFINITION

BIT NUMBER

D[7]

D[6]

D[5]

D[4:0]

Bit Name

N/A

IOUT OC

Warning

N/A

Default

Value

0 0000

TABLE 40. 0x7D STATUS TEMPERATURE REGISTER DEFINITION

BIT NUMBER

D[7]

D[6]

D[5]

D[4:0]

Bit Name

N/A

Warning

N/A

Default Value

0 0000

TABLE 41. 0x7E STATUS CML REGISTER DEFINITION

BIT NUMBER

D[7]

D[6]

D[5]

D[4:2]

D[1]

D[0]

Bit Name

USCMD USDATA PECERR

N/A

COMERR N/A

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