FN8389 datasheet(39/56 Pages) RENESAS

39 / 56 page

ISL28023

FN8389 Rev.6.03

Page 39 of 55

Oct 27, 2022

0XDD CONFIGURE INTERRUPTS (R/W)

The Configure Interrupt register is a read/writable word register

that controls the behavior of the two SMB alert pins. The

definition of the control bits within the Configure Interrupt

ALERT2_FEEDTHR D[14:12]

The Alert2_FeedThr bits determine whether the bit from each

alert comparator is digitally conditioned or not. The alert

comparators, digital filters and latching bits are the same for

both SMB alert channels. Table 32 defines the functionality of

the Alert2_FeedThr bits.

ALERT1_FEEDTHR D[11:9]

The Alert1_FeedThr bits determine whether the bit from each

alert comparator is digitally conditioned or not. The alert

comparators, digital filters and latching bits are the same for

both SMB alert channels. Table 33 defines the functionality of

the Alert1_FeedThr bits.

OC_FIL D[8:7]

The OC_FIL bits control the digital filter for the overcurrent

circuitry. The digital filter will prevent short duration events from

passing to the output pins. The filter is useful in preventing high

frequency power glitches from triggering a shutdown event. The

filter time delay ranges from 0µs to 8µs. An 8µs filter setting

requires an error event to be at least 8µs in duration before

passing the result to the SMB alert pins. There is one OC digital

filter for both SMB alert pins. Configuring OC_FIL bits will change

the OC digital filter setting for both SMB alert pins. See Table 34

for the filter selections.

UV_FIL D[6:5]

The UV_FIL bits control the digital filter for the undervoltage

circuitry. The digital filter will prevent short duration events from

passing to the output pins. The filter is useful in preventing high

frequency power glitches from triggering a shutdown event. The

filter time delay ranges from 0µs to 8µs. An 8µs filter setting

requires an error event to be at least 8µs in duration before

passing the result to the SMB alert pins. There is one UV digital

filter for both SMB alert pins. Configuring UV_FIL bits will change

the UV digital filter setting for both SMB alert pins. See Table 34

for the filter selections.

OV_FIL D[4:3]

The OV_FIL bits control the digital filter for the overvoltage

circuitry. The digital filter will prevent short duration events from

passing to the output pins. The filter is useful in preventing high

frequency power glitches from triggering a shutdown event. The

filter time delay ranges from 0µs to 8µs. An 8µs filter setting

requires an error event to be at least 8µs in duration before

passing the result to the SMB alert pins. There is one OV digital

filter for both SMB alert pins. Configuring OV_FIL bits will change

the OV digital filter setting for both SMB alert pins. See Table 34

for the filter selections.

OC_EN D[2]

The OC_EN enable bit controls the power to the overcurrent DAC

and comparator. Setting the bit to 1 enables the overcurrent

circuitry.

OV_EN D[1]

The OV_EN enable bit controls the power to the overvoltage DAC

and comparator. Setting the bit to 1 enables the overvoltage

circuitry.

UV_EN D[0]

The UV_EN enable bit controls the power to the undervoltage DAC

and comparator. Setting the bit to 1 enables the undervoltage

circuitry.

0XDE FORCE FEEDTHROUGH ALERT REGISTER (R/W)

The Force Feedthrough Alert Register is a read/writable byte

TABLE 31. 0xDD CONFIGURE INTERRUPT REGISTER DEFINITION

BIT

NUMBER

[15]

[14:12]

[11:9]

[8:7]

[6:5]

[4:3]

[2]

[1]

[0]

Bit Name N/A ALERT2

FeedTh

ALERT1

FeedTh

FIL

Default

Value

000

0 0

TABLE 32. Alert2_FeedThr BITS DEFINED

Alert2_FeedThr BITS

D[14:12]

BIT VAL

FUNCTIONALITY

D[14]

OV/OT Digitally Conditioned

1OV/OT Pass Through

D[13]

UV Digitally Conditioned

1UV Pass Through

D[13]

OC Digitally Conditioned

1OC Pass Through

TABLE 33. Alert1_FeedThr BITS DEFINED

Alert1_FeedThr Bits D[11:9] BIT VAL

FUNCTIONALITY

D[11]

OV/OT Digitally Conditioned

1OV/OT Pass Through

D[10]

UV Digitally Conditioned

1UV Pass Through

D[9]

OC Digitally Conditioned

1OC Pass Through

TABLE 34. DIGITAL GLITCH FILTER SETTINGS DEFINED

OC_FIL D[8:7]

UV_FIL D[6:5]

OV_FIL D[4:3]

FILTER TIME

(µs)

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