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LMKDB1120FS bảng dữ liệu(PDF) 97 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family
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LMKDB1120FS bảng dữ liệu(HTML) 97 Page - Texas Instruments

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Table 9-123. R91 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3:0
SLEWRATE_OPT_1
R/W
0h
There are four register assignments each storing a slew rate value
(chosen out of the 16 available slew rate values). This register bits
relate to the 1st option. Go to Programmable Output Slew Rate
section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)
9.5.20 R92 Register (Offset = 5Ch) [Reset = FAh]
R92 is shown in Table 9-124.
Return to the Summary Table.
Table 9-124. R92 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
SLEWRATE_OPT_4
R/W
Fh
There are four register assignments each storing a slew rate value
(chosen out of the 16 available slew rate values). This register bits
relate to the 4th option. Go to Programmable Output Slew Rate
section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)
www.ti.com
LMKDB1102, LMKDB1104, LMKDB1104FS, LMKDB1108, LMKDB1108FS
LMKDB1112, LMKDB1120, LMKDB1120FS
SNAS855G – NOVEMBER 2023 – REVISED MAY 2026
Copyright © 2026 Texas Instruments Incorporated
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