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HT9B95B bảng dữ liệu(PDF) 17 Page - Holtek Semiconductor Inc

tên linh kiện HT9B95B
Giải thích chi tiết về linh kiện  RAM Mapping 39×8 / 43×4 LCD Driver
PDF  32 Pages
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nhà sản xuất  HOLTEK [Holtek Semiconductor Inc]
Trang chủ  http://www.holtek.com
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HT9B95B bảng dữ liệu(HTML) 17 Page - Holtek Semiconductor Inc

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Rev. 1.10
17
November 25, 2015
HT9B95A/B/G
• Command Register Read Operation
The master reads the command register after setting
the slave address. Following the R/W bit (=”0”) is an
acknowledge bit and the register address byte which
is written to the internal address pointer. After the start
address of the read operation has been configured,
another START condition and the slave address
transferred on the bus followed by the R/W bit (=”1”).
Then the MSB of the data which was addressed
is transmitted first on the I2C bus. The C bit in the
register address byte can be set to “1” or “0”.
All command setting values are put together into
two command registers with the register addresses
of 23H and 24H or 27H and 28H when the
Command Register Read Operation is executed.
Each time the Command Register Read Operation
is executed, only one command register can be
read. To read all command registers, execute the
Command Register Read Operation twice with the
register address of 23H or 27H and 24H or 28H
respectively. The two command registers contents
are arranged in the following two registers and the
detailed definition are described in the “Command
Summary” section.
Part No.
Command
Register 1 Address
Command
Register 2 Address
HT9B95A
23h
24h
HT9B95B
HT9B95G
27h
28h
Command Register Address
• Command Register 1
Bit
7
6
5
4
3
2
1
0
Name — DB SR LV4 LV3 LV2 LV1 LV0
Bit 6
DB: Duty and Bias setting
Bit 5
SR: Software Reset Operation
Bit 4~0
LV4~LV0: LCD Voltage Adjustment
setting
• Command Register 2
Bit
7
6
5
4
3
2
1
0
Name FR1 FR0 PS1 PS0 W
D AP1 AP0
Bit 7~6
FR1~FR0: Frame Frequency setting
Bit 5~4
PS1~PS0: Power Save Mode setting
Bit 3
W: LCD Drive Waveform setting
Bit 2
D: Display On/Off setting
Bit 1~0
AP1~AP0: All pixels On/Off setting
ACK
P
Slave Address
S
0
1
1
1
1
1
0
0
Command Data byte
D7
D6
D5
D4
D3
D2
D1
D0
1st data
ACK
Device Address
S
0
1
1
1
1
1
0
1
ACK
Command Register Address
A0
A1
A2
A3
A4
A5
0
C
NACK
P
C bit
Write
W
R/
Read
W
R/
Command Register Read Operation



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