ADS5560 datasheet(3/53 Pages) TI

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ABSOLUTE MAXIMUM RATINGS

(1)

RECOMMENDED OPERATING CONDITIONS

ADS5560

ADS5562

www.ti.com ....................................................................................................................................................................................................... SLWS207 – MAY 2008

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

AVDD

Supply voltage range

–0.3 V to 3.9

DRVDD

Supply voltage range

–0.3 V to 3.9

Voltage between AGND and DRGND

-0.3 to 0.3

Voltage between AVDD to DRVDD

-0.3 to 3.3

Voltage applied to VCM pin (in external reference mode)

-0.3 to 1.8

Voltage applied to analog input pins

–0.3 V to minimum (3.6, AVDD + 0.3 V)

Operating free-air temperature range

–40 to 85

°C

Tjmax

Operating junction temperature range

125

°C

TSTG

Storage temperature range

–65 to 150

°C

Lead temperature 1,6 mm (1/16") from the case for 10 seconds

220

°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

SUPPLIES AND REFERENCES

AVDD

Analog supply voltage

3.3

3.6

DRVDD Digital supply voltage

3.3

3.6

ANALOG INPUTS

Differential input voltage range (with default fine gain=1 dB)

3.56

VPP

Input common-mode voltage

1.5 ±0.1

Voltage applied on VCM in external reference mode

1.5

±0.05

CLOCK INPUT

Sample rate

DEFAULT SPEED mode

> 30

MSP

ADS5562

LOW SPEED mode (1)

MSP

DEFAULT SPEED mode

> 30

MSP

ADS5560

LOW SPEED mode

MSP

Sine wave, LVPECL,

Supported clock waveform formats

LVDS, LVCMOS

Clock amplitude, ac-coupled, differential (VCLKP - VCLKM)

0.4

VPP

Clock duty cycle

45%

50%

55%

DIGITAL OUTPUTS

Maximum external load capacitance from each output pin to DRGND (LVDS and CMOS

modes)

Differential external load resistance between the LVDS output pairs (LVDS mode)

100

Ω

Operating free-air temperature

-40

°C

(1)

See Low sampling frequency operation in application section for details.

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