ADS5560 datasheet(39/53 Pages) TI

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Clock Input

S0166-05

CLKP

VCM

5kW

CLKM

VCM

ADS556x

ADS5560

ADS5562

www.ti.com ....................................................................................................................................................................................................... SLWS207 – MAY 2008

For low sampling frequencies (below 30 MSPS), the ADC must be put in the LOW SPEED mode. This mode can

be entered by

• setting the register bit <LOW SPEED> (Table 12) through the serial interface, OR

• tying the SCLK pin to high (see Table 4) using the parallel configuration.

ADS556X clock input can be driven with either a differential clock signal or a single-ended clock input, with little

or no difference in performance between both configurations. The common-mode voltage of the clock inputs is

set to VCM using internal 5-k

Ω resistors that connect CLKP and CLKM to VCM, as shown in Figure 54.

Figure 54. Clock Inputs

For the best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to

common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with

0.1-

µF capacitors, as shown in Figure 55.

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