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ADS5560 bảng dữ liệu(PDF) 13 Page - Texas Instruments

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tên linh kiện ADS5560
Giải thích chi tiết về linh kiện  16-BIT, 40/80 MSPS ADCs WITH DDR LVDS/CMOS OUTPUTS
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Trang chủ  http://www.ti.com
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ADS5560 bảng dữ liệu(HTML) 13 Page - Texas Instruments

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DESCRIPTION OF PARALLEL PINS
SERIAL INTERFACE
ADS5560
ADS5562
www.ti.com ....................................................................................................................................................................................................... SLWS207 – MAY 2008
Table 4. SCLK Control Pin
SCLK
DESCRIPTION
0
DEFAULT SPEED mode - Use for sampling frequencies > 30 MSPS.
DRVDD
LOW SPEED mode Enabled - Use for sampling frequencies
≤ 30 MSPS.
Table 5. SDATA Control Pin
SDATA
DESCRIPTION
0
Normal operation (Default)
DRVDD
STANDBY. This is a global power down, where ADC, internal references and the output buffers are powered down.
Table 6. SEN Control Pin
SEN
With CMOS interface
0
CLKOUT Rising edge later by (3/36)Ts
CLKOUT Falling edge later by (3/36)Ts
(3/8)DRVDD
CLKOUT Rising edge later by (5/36)Ts
CLKOUT Falling edge later by (5/36)Ts
(5/8)DRVDD
CLKOUT Rising edge earlier by (3/36)Ts
CLKOUT Falling edge earlier by (3/36)Ts
DRVDD
Default CLKOUT position
With LVDS interface
0
CLKOUT Rising edge later by (7/36)Ts
CLKOUT Falling edge later by (6/36)Ts
(3/8)DRVDD
CLKOUT Rising edge later by (7/36)Ts
CLKOUT Falling edge later by (6/36)Ts
(5/8)DRVDD
CLKOUT Rising edge later by (3/36)Ts
CLKOUT Falling edge later by (3/36)Ts
DRVDD
Default CLKOUT position
Table 7. DFS Control Pin
DFS
DESCRIPTION
0
2's complement data and DDR LVDS output (Default)
(3/8)DRVDD
2's complement data and parallel CMOS output
(5/8)DRVDD
Offset binary data and parallel CMOS output
DRVDD
Offset binary data and DDR LVDS output
Table 8. MODE Control Pin
MODE
DESCRIPTION
0
Internal reference
(3/8)AVDD
External reference
(5/8)AVDD
External reference
AVDD
Internal reference
The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device
power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET
(of width greater than 10 ns).
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): ADS5560 ADS5562



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