SH-2A datasheet(13/501 Pages) RENESAS

13 / 501 page

Rev. 3.00 Jul 08, 2005 page xiii of xiv

8.2

Slots and Pipeline Flow .................................................................................................... 339

8.3

Instruction Execution and Parallel Execution Capability ................................................. 341

8.3.1

Details of Resource Contention ........................................................................... 342

8.3.2

Details of Contention Due to Wait for Result of Previously Issued Instruction .. 345

8.3.3

Details of Register Contention and Flag Contention ........................................... 345

8.3.4

Details of Contention Due to Multi-Cycle Instruction......................................... 347

8.3.5

Details of Contention Due to 32-Bit Instruction.................................................. 348

8.3.6

Details of Contention Due to Instruction that Uses FPSCR ................................ 349

8.3.7

Details of Contention Due to Branch Instruction................................................. 350

8.4

Number of Instruction Execution States ........................................................................... 351

8.5

Effect of Memory Load Instruction on Pipeline ............................................................... 352

8.6

Contention Due to FPU..................................................................................................... 353

8.7

Contention Due to Multiplier............................................................................................ 360

8.8

Programming Strategy ...................................................................................................... 364

8.9

Pipeline Operations for Each Instruction .......................................................................... 364

8.9.1

Data Transfer Instructions ................................................................................... 378

8.9.2

Arithmetic Operation Instructions ....................................................................... 390

8.9.3

Logical Operation Instructions ............................................................................ 404

8.9.4

Shift Instructions.................................................................................................. 412

8.9.5

Branch Instructions.............................................................................................. 414

8.9.6

System Control Instructions................................................................................. 422

8.9.7

Exception Handling ............................................................................................. 443

8.9.8

Floating-Point Instructions and FPU-Related CPU Instructions.......................... 448

8.10 Simple Method of Calculating Required Number of Clock Cycles.................................. 475

Appendix A SH-2A/SH2A-FPU Parallel Execution................................................. 479

Appendix B Programming Guidelines (Using MOVI20 and MOVI20S) .......... 483

SH-2A bảng dữ liệu(PDF) 13 Page - Renesas Technology Corp

SH-2A bảng dữ liệu(HTML) 13 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL