SH-2A datasheet(49/501 Pages) RENESAS

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Section 4 Instruction Features

Rev. 3.00 Jul 08, 2005 page 35 of 484

REJ09B0051-0300

Table 4.3

T Bit

SH-2A/SH2A-FPU CPU

Description

Example for Other CPU

CMP/GE R1,R0

TRGET0

TRGET1

T bit is set when R0 ≥ R1. The

program branches to TRGET0

when R0 ≥ R1 and to TRGET1

when R0 < R1.

CMP.W R1,R0

BGE

TRGET0

BLT

TRGET1

ADD

#–1,R0

CMP/EQ #0,R0

TRGET

T bit is not changed by ADD. T

bit is set when R0 = 0. The

program branches if R0 = 0.

SUB.W #1,R0

BEQ

TRGET

(10) Immediate Data

Byte immediate data is located in instruction code. Word or longword immediate data is not input

via instruction codes but is stored in a memory table. The memory table is accessed by an

immediate data transfer instruction (MOV) using the PC relative addressing mode with

displacement.

With the SH-2A/SH2A-FPU, immediate data of 17 to 28 bits can be located in an instruction code.

However, for immediate data of 21 to 28 bits, an OR instruction must be executed after a register

transfer.

Table 4.4

Referencing by Means of Immediate Data

Type

SH-2A/SH2A-FPU CPU

Example for Other CPU

8-bit immediate

MOV

#H'12,R0

MOV.B

#H'12,R0

16-bit immediate

MOVI20

#H'1234, R0

MOV.W #H'1234,R0

20-bit immediate

MOVI20

#H'12345, R0

MOV.L

#H'12345,R0

28-bit immediate

MOVI20S #H'12345, R0

#H'67, R0

MOV.L

#H'1234567,R0

32-bit immediate

MOV.L

@(disp,PC),R0

. . . . . . . . . . .

.DATA.L

H'12345678

MOV.L

#H'12345678,R0

Note: Immediate data is referenced by @(disp,PC).

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