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39 / 501 page ![]() Section 3 Exception Handling Rev. 3.00 Jul 08, 2005 page 25 of 484 REJ09B0051-0300 3.6 Interrupts 3.6.1 Interrupt Sources Interrupt exception handling can be initiated by an NMI, a user break, the H-UDI, an external interrupt, or an on-chip peripheral module, as shown in table 3.6. Table 3.6 Interrupt Sources Type Request Source Number of Sources NMI NMI pin (external input) 1 User break User break controller 1 H-UDI User debug interface 1 External interrupt (IRQ), on-chip peripheral module External interrupt pin, on-chip peripheral module See Note Each interrupt source is assigned a different vector number and vector table offset. For details of vector numbers and vector table address offsets, see “Interrupt Exception Vectors and Priority” in the Interrupt Controller section of the hardware manual for the relevant product. Note: For details and numbers of external interrupts (IRQ) and on-chip peripheral module request sources, see “Interrupt Sources” in the Interrupt Controller section of the hardware manual for the relevant product. 3.6.2 Interrupt Priority Interrupt sources are assigned priority levels. If a number of interrupts occur simultaneously (multiple interruption), the priority order is determined by the interrupt controller (INTC) and exception handling is initiated accordingly. Interrupt source priority levels are expressed as values from 0 to 16, with 0 representing the lowest priority level and 16 the highest. The NMI interrupt is the highest-priority interrupt at level 16; it cannot be masked and is always accepted. The user break interrupt and H-UDI are assigned priority level 15. The priority level of IRQ interrupts and on-chip peripheral module interrupts can be set as desired in the interrupt priority level setting registers of the INTC (see table 3.7). Priority levels 0 to 15, but not 16, can be set. For details of the interrupt priority level setting registers, see the Interrupt Controller section of the hardware manual for the relevant product. |
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