M36DR432BD datasheet(24/52 Pages) STMICROELECTRONICS

24 / 52 page

M36DR432AD, M36DR432BD

24/52

SRAM COMPONENT

The SRAM is a 4 Mbit (256Kb x16) low-power con-

sumption memory array with low VDDS data reten-

tion.

SRAM Operations

The following operations can be performed using

the appropriate bus cycles: Read Array, Write Ar-

ray, Output Disable, Power Down (see Table 2).

Read. Read operations are used to output the

contents of the SRAM Array. The SRAM is in Read

mode whenever Write Enable (WS) is at VIH with

Output Enable (GS) at VIL, Chip Enable ES and

UBS, LBS combinations are asserted.

Valid data will be available at the output pins within

tAVQV after the last stable address, provided that

GS is Low and ES is Low. If Chip Enable or Output

Enable access times are not met, data access will

be measured from the limiting parameter (tELQV or

tGLQV) rather than the address. Data out may be

indeterminate at tELQX and tGLQX, but data lines

will always be valid at tAVQV (see Table 23, Figures

17 and 18).

Write. Write operations are used to write data in

the SRAM. The SRAM is in Write mode whenever

the WS and ES pins are at VIL. Either the Chip En-

able input (ES) or the Write Enable input (WS)

must be de-asserted during address transitions for

subsequent write cycles. Write begins with the

concurrence of Chip Enable being active and WS

at VIL. A Write begins at the latest transition

among ES going to VIL and WS going to VIL.

Therefore, address setup time is referenced to

Write Enable and Chip Enable as tAVWL and tAVEL

respectively, and is determined by the latter occur-

ring edge. The Write cycle can be terminated by

the rising edge of ES or the rising edge of WS,

whichever occurs first.

If the Output is enabled (ES=VIL and GS=VIL),

then WS will return the outputs to high impedance

within tWLQZ of its falling edge. Care must be taken

to avoid bus contention in this type of operation.

Data input must be valid for tDVWH before the ris-

ing edge of Write Enable, or for tDVEH before the

rising edge of ES, whichever occurs first, and re-

main valid for tWHDX and tEHAX (see Table 24, Fig-

ure 20, 22, 24).

Standby/Power-Down. The SRAM chip has a

Chip Enable power-down feature which invokes

an automatic standby mode (see Table 23, Figure

19) whenever either Chip Enable is de-asserted

(ES=VIH).

Data Retention. The SRAM data retention per-

formances as VDDS go down to VDR are described

in Table 25 and Figure 24. In ES controlled data

retention mode, minimum standby current mode is

entered when ES

≥ VDDS –0.2V.

Output Disable. The data outputs are high im-

pedance when the Output Enable (GS) is at VIH

with Write Enable (WS) at VIH.

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