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M36DR432BD bảng dữ liệu(PDF) 22 Page - STMicroelectronics |
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M36DR432BD bảng dữ liệu(HTML) 22 Page - STMicroelectronics |
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22 / 52 page ![]() M36DR432AD, M36DR432BD 22/52 Error Bit (DQ5). The Error Bit can be used to identify if an error occurs during a program or erase operation. The Error Bit is set to ‘1’ when a program or erase operation has failed. When it is set to ‘0’ the pro- gram or erase operation was successful. If any Program command is used to try to set a bit from ‘0’ to ‘1’ Status Register Error bit DQ5 will be set to ‘1’, only if VPP is in the range of 11.4V to 12.6V. The Error Bit is reset by a Read/Reset command. Erase Timer Bit (DQ3). The Erase Timer bit is used to indicate the timeout period for an erase operation. When the last block Erase command has been en- tered to the Command Interface and it is waiting for the erase operation to start, the Erase Timer Bit is set to ‘0’. When the erase timeout period is fin- ished, DQ3 returns to ‘1’, (80µs to 120µs). DQ0, DQ1 and DQ4 are reserved for future use and should be masked. Table 11. Polling and Toggle Bits Mode DQ7 DQ6 DQ2 Program DQ7 Toggle 1 Erase 0 Toggle N/A Erase Suspend Read (in Erase Suspend block) 1 1 Toggle Erase Suspend Read (outside Erase Suspend block) DQ7 DQ6 DQ2 Erase Suspend Program DQ7 Toggle 1 |
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