ST7FOXF1 datasheet(48/226 Pages) STMICROELECTRONICS

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Supply, reset and clock management

ST7FOXF1, ST7FOXK1, ST7FOXK2

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6.5.4

RC Control Register Low (RCCRL)

Reset value: 011x 0x00 (xxh)

Bit 7 = Reserved, must be kept cleared

Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits

These bits, as well as CR[9:2] bits in the RCCRH register must be written immediately

after reset to adjust the RC oscillator frequency. Refer to Section 6.1.1: Internal RC

oscillator on page 34.

Bit 4 = WDGRF Watchdog Reset flag

This bit indicates that the last reset was generated by the watchdog peripheral. It is set by

hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to

ensure a stable cleared state of the WDGRF flag when CPU starts). The WDGRF and the

LVDRF flags areis used to select the reset source (see Table 10: Reset source selection on

page 48).

Bit 3 = Reserved, must be kept cleared

Bit 2 = LVDRF LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by

hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled

by option byte, the LVDRF bit value is undefined.

The LVDRF flag is not cleared when another RESET type occurs (external or

watchdog), the LVDRF flag remains set to keep trace of the original failure.

In this case, a watchdog reset can be detected by software while an external reset can

not.

Bits 1:0 = Reserved, must be kept cleared

CR1

CR0

WDGRF

LVDRF

Read/write

Table 10.

Reset source selection

RESET source

LVDRF

WDGRF

External RESET pin

Watchdog

LVD

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