ST7FOXF1 datasheet(167/226 Pages) STMICROELECTRONICS

167 / 226 page

ST7FOXF1, ST7FOXK1, ST7FOXK2

On-chip peripherals

167/226

Figure 79.

Single master / multiple slave configuration

10.6.7

Low power modes

10.6.8

Interrupts

Note:

The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

MISO

MOSI

MISO

SCK

Slave

Device

Slave

Device

Slave

Device

Slave

Device

Master

Device

Table 50.

Low power mode descriptions

Mode

Description

WAIT

No effect on SPI.

SPI interrupt events cause the device to exit from WAIT mode.

HALT

SPI registers are frozen.

In HALT mode, the SPI is inactive. SPI operation resumes when the device is

woken up by an interrupt with “exit from HALT mode” capability. The data

received is subsequently read from the SPIDR register when the software is

running (interrupt vector fetching). If several data are received before the

wakeup event, then an overrun error is generated. This error can be detected

after the fetch of the interrupt routine that woke up the Device.

Table 51.

Interrupt events

Interrupt event

Event

flag

Enable control

bit

Exit from Wait

Exit from Halt

SPI End of Transfer Event

SPIF

SPIE

Yes

Master Mode Fault Event

MODF

Overrun Error

OVR

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