ST7FOXF1 datasheet(101/226 Pages) STMICROELECTRONICS

101 / 226 page

ST7FOXF1, ST7FOXK1, ST7FOXK2

On-chip peripherals

101/226

This bit is read/write by software and cleared by hardware after a reset. This bit enables

the One Pulse feature for PWM2 and PWM3 (only available for PWM3CSR)

0: One Pulse mode disable for PWM2/3.

1: One Pulse mode enable for PWM2/3.

Bit 2 = OPEDGE One Pulse Edge Selection bit

This bit is read/write by software and cleared by hardware after a reset. This bit selects

the polarity of the LTIC signal for One Pulse feature. This bit will be effective only if

OP_EN bit is set (only available for PWM3CSR)

0: Falling edge of LTIC is selected.

1: Rising edge of LTIC is selected.

Bit 1 = OPx PWMx Output Polarity bit

This bit is read/write by software and cleared by hardware after a reset. This bit selects

the polarity of the PWM signal.

0: The PWM signal is not inverted.

1: The PWM signal is inverted.

Bit 0 = CMPFx PWMx Compare flag

This bit is set by hardware and cleared by software by reading the PWMxCSR register.

It indicates that the upcounter value matches the Active DCRx register value.

0: Upcounter value does not match DCRx value.

1: Upcounter value matches DCRx value.

Break control register 1 (BREAKCR1)

Reset value: 0000 0000 (00h)

Bit 7 = BR1SEL Break 1 input selection bit (only available on ST7FOXK2, reserved for

ST7FOXF1/ST7FOXK1)

This bit is read/write by software and cleared by hardware after reset. It selects the

active Break 1 signal from external BREAK1 pin and the output of the comparator.

0: External BREAK1 pin is selected for break mode.

1: Comparator 1 output is selected for break mode.

Bit 6 = BR1EDGE Break 1 input edge selection bit (BREDGE on ST7FOXF1/ST7FOXK1)

This bit is read/write by software and cleared by hardware after reset. It selects the

active level of Break 1 signal.

0: Low level of Break 1selected as active level

1: High level of Break 1selected as active level

BR1SEL

BR1EDGE

BA1

BP1EN

PWM3

PWM2

PWM1

PWM0

Read/write

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