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APM32E103CET6-R bảng dữ liệu(PDF) 51 Page - Geehy Semiconductor Co., Ltd.

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Pag e 50
Table36 Output Drive Current Characteristics (test condition VDD=2.7~3.6V, TA=-40~105
℃)
Symbol
Parameter
Conditions
Minimum
value
Maximum
value
Unit
VOL
Output low level voltage for an I/O pin when
8 pins are sunk at same time
IIO = +8mA
2.7V<VDD<3.6V
-
0.49
V
VOH
Output high level voltage for an I/O pin when
8 pins are sourced at same time
VDD-0.4
-
VOL
Output low level voltage for an I/O pin when
8 pins are sunk at same time
IIO = +20mA
2.7V<VDD<3.6V
-
1.50
V
VOH
Output high level voltage for an I/O pin when
8 pins are sourced at same time
VDD-1.2
-
5.9.2.
NRST pin characteristics
The NRST pin input drive adopts CMOS process, which is connected with a permanent pull-up
resistor RPU.
Table 37 NRST Pin Characteristics (test condition VDD=3.3V, TA=-40~105
℃)
Symbol
Parameter
Conditions
Minimum
value
Typical
value
Maximum
value
Unit
VIL(NRST)
NRST low level input voltage
-
-0.5
-
0.8
V
VIH(NRST)
NRST high level input voltage
-
2
-
VDD+0.5
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
-
-
200
-
mV
RPU
Weak pull-up equivalent
resistance
VIN = VSS
30
40
50
kΩ
Note: It is obtained from a comprehensive evaluation and is not tested in production.
5.10.
Communication peripherals
5.10.1.
I2C peripheral characteristics
To achieve maximum frequency of I2C in standard mode, fPCLK1 must be greater than 2MHz. To
achieve maximum frequency of I2C in fast mode, fPCLK1 must be greater than 4MHz.
Table 38 I2C Interface Characteristics (TA=25
℃, VDD=3.3V)
Symbol
Parameter
Standard I2C
Fast I2C
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
μs
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
tsu(SDA)
SDA setup time
250
-
100
-
ns
th(SDA)
SDA data hold time
-
3450
-
900
tr(SDA)/tr(SCL)
SDA and SCL rise time
-
1000
-
300
tf(SDA)/tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
Start condition hold time
4.0
-
0.6
-
μs



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