APM32E103CET6-R datasheet(46/79 Pages) GEEHY

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Table 29 Power Consumption in Sleep Mode when the Program is Executed in RAM

Parameter

Conditions

fHCLK

Typical value (1)

Maximum value (1)

TA=25

℃，VDD=3.3V

TA=105

℃，VDD=3.6V

IDDA

(μA)

IDD(mA）

IDDA

(μA)

IDD(mA)

Power

consumption

in sleep mode

HSECLK bypass (2) , enabling all

peripherals

96MHz

215.97

14.06

250.92

15.59

72MHz

165.85

10.84

196.02

10.74

48MHz

119.17

7.44

142.13

7.71

36MHz

96.50

5.77

117.08

5.84

24MHz

119.21

3.93

136.05

4.35

16MHz

89.36

2.77

109.38

3.14

8MHz

17.73

1.6

23.65

2.01

HSECLK bypass (2) , turning off all

peripherals

96MHz

215.53

3.12

248.57

3.64

72MHz

165.75

2.44

192.92

3.14

48MHz

118.99

1.80

141.57

2.24

36MHz

96.46

1.44

117.39

1.94

24MHz

119.11

1.15

142.46

1.63

16MHz

89.21

0.94

109.67

1.36

8MHz

17.71

0.66

23.00

1.14

HSICLK (2) , enabling all

peripherals

64MHz

237.15

9.31

265.75

9.74

48MHz

206.68

7.13

232.94

7.56

36MHz

184.39

5.44

209.27

5.87

24MHz

163.18

3.51

187.51

4.27

16MHz

177.19

2.45

201.95

3.12

8MHz

102.68

1.28

122.82

1.91

HSICLK (2) , turning off all

peripherals

64MHz

237.19

1.93

266.13

2.54

48MHz

206.65

1.47

233.12

2.10

36MHz

184.36

1.13

209.35

1.80

24MHz

163.10

0.82

187.67

1.50

16MHz

177.13

0.62

202.00

1.29

8MHz

102.60

0.36

122.86

1.03

Note:

(1) It is obtained from a comprehensive evaluation and is not tested in production.

(2) The external clock is 8MHz, and when fHCLK>8MHz, turn on PLL, otherwise, turn off PLL

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