ESP32-P4 datasheet(71/93 Pages) ESPRESSIF

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4 Functional Description

full-speed (FS) and 1.5 Mbit/s low-speed (LS) data rates of the USB 2.0 specification. The Host Negotiation

Protocol (HNP) and the Session Request Protocol (SRP) are also supported.

Feature List

General Features

• USB 2.0 specification, OTG Revision 1.3 and OTG Revision 2.0 specifications

• USB 2.0 full-speed and low-speed data rates

• HNP and SRP as A-device or B-device

• Dynamic FIFO (DFIFO) sizing, maximum to 1 KB

• Multiple modes of memory access

– Scatter/Gather DMA mode

– Buffer DMA mode

– Slave mode

• Two integrated transceivers

Device Mode Features

• Endpoint 0 always present, bi-directional, consisting of EP0 IN and EP0 OUT

• Six additional endpoints 1–6, configurable as IN or OUT

• Maximum of five IN endpoints concurrently active at any time, including EP0 IN

• All OUT endpoints share a single RX FIFO

• Each IN endpoint has a dedicated TX FIFO

Host Mode Features

• Eight host channels

• RX FIFO: shared by all periodic and non-periodic transactions

• Two TX FIFO:

– One shared by all non-periodic transactions

– One shared by all periodic transactions

• All of the above FIFOs share a 1 KB RAM.

• The size of each FIFO is configurable, with a maximum of 1 KB.

Pin Assignment

The pins connected to D+ and D- signals for two pairs of USB PHY are multiplexed with GPIO24–GPIO25 and

GPIO26–GPIO27. The USB 2.0 Full-Speed OTG interface can use each of them. By default, the pins are

multiplexed with GPIO26–GPIO27. In addition, the functionalities of USB_D- and USB_D+ can be

exchanged.

Other signals can be routed to any GPIOs via the GPIO matrix.

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ESP32-P4 Series Datasheet v0.5

ESP32-P4 bảng dữ liệu(PDF) 71 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.