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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TMS320VC5506 bảng dữ liệu(PDF) 63 Page - Texas Instruments |
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TMS320VC5506 bảng dữ liệu(HTML) 63 Page - Texas Instruments |
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63 / 120 page  Functional Overview 63 October 2006 − Revised January 2008 SPRS375C 3.11.1 IFR and IER Registers The IFR0 (Interrupt Flag Register 0) and IER0 (Interrupt Enable Register 0) bit layouts are shown in Figure 3−17. 15 14 13 12 11 10 9 8 DMAC5 DMAC4 XINT2 RINT2 INT3/ WDTINT Reserved DMAC1 USB R/W R/W R/W R/W R/W R/W-0† R/W R/W 76 54 32 10 XINT1 RINT1 RINT0 TINT0 INT2 INT0 Reserved R/W R/W R/W R/W R/W R/W Legend: R = Read, W = Write, n = value after reset † Always write zero. Figure 3−17. IFR0 and IER0 Bit Locations Table 3−33. IFR0 and IER0 Register Bit Fields BIT FUNCTION NUMBER NAME FUNCTION 15 DMAC5 DMA channel 5 interrupt flag/mask bit 14 DMAC4 DMA channel 4 interrupt flag/mask bit 13 XINT2 This bit is used as the McBSP2 transmit interrupt flag/mask bit. 12 RINT2 McBSP2 receive interrupt flag/mask bit. 11 INT3/WDTINT This bit is used as either the external user interrupt 3 flag/mask bit, or the watchdog timer interrupt flag/mask bit.† 10 − Reserved 9 DMAC1 DMA channel 1 interrupt flag/mask bit 8 USB USB interrupt flag/mask bit. 7 XINT1 This bit is used as the McBSP1 transmit interrupt flag/mask bit. 6 RINT1 McBSP1 receive interrupt flag/mask bit. 5 RINT0 McBSP0 receive interrupt flag bit 4 TINT0 Timer 0 interrupt flag bit 3 INT2 External interrupt 2 flag bit 2 INT0 External interrupt 0 flag bit 1−0 − Reserved for future expansion. These bits should always be written with 0. † It is possible to have active interrupts simultaneously from both the external INT3 source and the watchdog timer. When an interrupt is detected in this bit, the watchdog timer status register should be polled to determine if the watchdog timer is the interrupt source. |
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