Copyright © 2016

Microsemi

Page 7

Rev. 1.4, July 2017

CPG

– PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70211

PD Controller with Switching Regulator for

AF/AT/UPOE/HDBaseT/4-pair PoE Applications

Pin

Number

Designator

Description

28

CSN

The negative input of the internal current-sense voltage amplifier. Note that the common-

mode range of the differential current-sense amplifier is 2V and its gain is 5. We can use this

for high-side current sensing up to 2V. It is then placed on the (steady) output side of a Buck

inductor, and the max output voltage is 1.8V for using this type of sensing. Ensure that CSN

is at a lower voltage compared to the positive input of the current-sense amplifier (CSP).

Current sensing can also be implemented in a more basic fashion for “low-side” sensing,

with a resistor in the return (ground) of the Buck. In that case CSN is shown connected to IC

ground. However, to avoid noise from ground bounce, it is best to route this on the PCB in

Kelvin manner to the lower end of the sense resistor. This is important because the peak

operating voltage on the sense resistor is only 200mV and PCB-related noise can cause jitter

in the switching waveform in current-mode control.

29

CSP

The positive input of the internal current-sense voltage amplifier. See discussion for Pin 28

(CSN) above. Note that the output of the current-sense amplifier is amplified 5 times. So a

0.2V current-sense voltage translates to a 1V swing at the input of the PWM comparator.

Higher voltages lead to hiccup mode protection.

30

PG

This stands for Primary Gate driver. We can use this to drive the main FET, and it has a 5 or

10Ω limiting drive resistor switched between a voltage close to VCC rail and the IC ground.

For guaranteeing proper shutdown during OFF time, it is necessary to add a 470k resistor

from PG to VINS, as shown in Figure 1.

31

VH

Internal rail of -5V with respect to VCC, brought out only for decoupling purposes. Connect a

0.1µF ceramic cap very close, from this pin to VAUX_VCC pin.

32

VAUX_VCC

Auxiliary voltage rail from front-end to the VCC (supply) input of the PWM section. The

front-end provides a few mA of startup current for the PWM controller (at typically 10.5V).

Signal is referenced to VPN_OUT and is activated once front end power up sequence is end.

After initial startup of PWM section, a bias winding can be connected to this pin through a

diode, to sustain the PWM section.

33

WA_EN

While this input is low (referenced to VPN_IN) the chip work according to internal flow

diagram. When this input is high, it enable wall adapter feature. Place 100nF/10V capacitor

from WA_EN to VPN_IN pins, locate it close to device. When WA_EN is not used, connect it

to VPN_IN. For further information, refer to External source connected to PD device output.

34

4P_HD_FLAG

Open Drain Output. The pin gets actively pulled low when a 4-pair HDBaseT PD-PSE

mutually identify each other via classification. There is a minimum 80 ms delay from the

moment that the input capacitor is fully charged to this signal activity. Signal is referenced

to VPN_OUT

35

VPP

Upper rail of the incoming PSE voltage rail – from the positive terminal of the two OR-ed

bridge rectifiers (the corresponding lower PoE rail is VPN_IN)

36

RDET

Internally connects to VPN_IN during detection phase and disengages after it is over. A

25KΩ (or 24.9K), 1% resistor is connected between this pin and VPP

37

EPAD

Connected on PCB plane to VPN_IN