Copyright © 2016

Microsemi

Page 3

Rev. 1.4, July 2017

CPG

– PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70211

PD Controller with Switching Regulator for

AF/AT/UPOE/HDBaseT/4-pair PoE Applications

Pin Description (PD70211)

Pin

Number

Designator

Description

1

SUPP_S1

Input pin for sensing the voltage on the diode bridge connected to the data pairs. This pin

along with the SUPP_S2 pin can be used to distinguish between 2-pair and 4-pair operation.

(For PSEs that operate in 4 pairs but do not generate the classification procedure on both

pair but one pair only). Signal is referenced to VPN_IN. Place a 10k resistor in the input of

this pin.

2

SUPP_S2

Input pin for sensing the voltage on the diode bridge connected to the data pairs. This pin

along with the SUPP_S1 pin can be used to distinguish between 2-pair and 4-pair operation.

(For PSEs that operate in 4 pairs but do not generate the classification procedure on both

pair but one pair only) . Signal is referenced to VPN_IN. Place a 10k resistor in the input of

this pin.

3

4P_AT_FLAG

Open Drain Output. The pin gets actively pulled low when a 4-pair version of a (non-

standard) Type 2 PD-PSE mutually identifies each other via classification. There is a

minimum 80 ms delay from the moment that the input capacitor is fully charged to this

signal activity. Signal is referenced to VPN_OUT

4

RREF

Bias current resistor. A 60.4k, 1% resistor is connected between RREF and IC ground

(VPN_IN)

5

RCLASS

Sets the Class of the PD. Connect RCLASS (programming resistor) between this pin and IC

ground (VPN_IN). Allowed values are 133 Ω, 69.8 Ω, 45.3 Ω, and 30.9 Ω for Class 1, 2, 3, and

4 respectively. If RCLASS is not present, the PD will draw up to 3 mA during classification,

thus indicating Class 0 (default Type 1) to the PSE. Signal is referenced to VPN_IN

6

HD_FLAG

Open Drain Output. The pin gets actively pulled low when a 2-pair HDBaseT PD-PSE

mutually identify each other via classification. There is a minimum 80 ms delay from the

moment that the input capacitor is fully charged to this signal activity. Signal is referenced

to VPN_OUT

7

AT_FLAG

Open Drain Output. This pin gets actively pulled low when a Type 2 PD-PSE mutually

identifies each other via classification. There is a minimum 80 ms delay from the moment

that the input capacitor is fully charged to this signal activity. Signal is referenced to

VPN_OUT

8, 9

VPN_IN

Lower rail of the incoming PSE voltage rail – from the negative terminal of the two OR-ed

bridge rectifiers (the corresponding upper PoE rail is VPP)

10, 11

VPN_OUT

This is in effect, the switched ground for establishing continuity to the PWM section after

successful detection, classification, and Power-up. It is connected to the Power ground and

PWM controller IC’s ground plane of the DC-DC converter section