Copyright © 2016

Microsemi

Page 6

Rev. 1.4, July 2017

CPG

– PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70211

PD Controller with Switching Regulator for

AF/AT/UPOE/HDBaseT/4-pair PoE Applications

Pin

Number

Designator

Description

21

COMP

This is the output of the internal error amplifier, and the input of the PWM comparator. It is

brought out to support isolated topologies because in such cases, there is an error amplifier

already present on the Secondary side (for example a TL431 or equivalent). Therefore we

want to bypass the error amplifier of the converter section. On the other hand, in non-

isolated topologies, we want to use the error amplifier of the converter. We can do that

directly, or through the differential voltage amplifier stage.

22

DAO

This is the output of the internal differential voltage amplifier (gain = 7). When this

amplifier is used, we connect DAO to the feedback pin (FB). We have part of the

compensation network between the two pins, and this network is typical of any Type 3 error

amplifier input, with or without a differential amplifier present.

23

FB

This is the feedback pin of the IC. It is internally compared to a 1.2V reference. If the

internal error amplifier is not used and the COMP pin is being used to inject the error signal

(as in isolated topologies), the FB pin can be either tied high (to VDD), or connected to

COMP.

24

GND

This is the IC ground. In more detail this is the analog (quiet) ground of the IC. Pin 20 is the

Power ground (PGND). Typically, we can connect the analog ground and PGND together on

a copper island on the component side, and then connect that through several vias very

close to the chip on to a large ground plane which extends up to the lower side of the

current sense resistor. All chip decoupling can then be very simply with respect to the

copper island on the component side.

25

VL

This is created by an internal LDO and basically provides a housekeeping rail for the IC itself,

which is 5V with respect to the IC ground. A 1µF ceramic cap placed close to this pin,

connected to IC ground is recommended for proper decoupling. This pin can also provide

up to 5mA for external circuitry if required, thermal aspects (IC dissipation) being

considered.

26

SG

Secondary Gate driver. We can use this to drive a synchronous FET or an active clamp FET.

It is derived from VCC (~ 12V), and has a 10Ω limiting resistor. So it can be used to drive a

Gate-drive transformer directly. It is usually complementary to the Primary Gate driver pin

(PG). But there is a typical 110ns blanking time between the two to prevent cross-

conduction. SG is held firmly low in pulse-skip mode (if allowed). It is also low during soft-

start. It allows forced PWM (continuous conduction) mode by allowing negative inductor

currents. It does not support diode-emulation mode (discontinuous conduction mode).

However, in pulse-skip mode, since SG stays OFF, the converter automatically lapses into

discontinuous conduction mode through the body-diode of the synchronous FET. We can

leave this pin floating if unused.

27

PGND

Power ground (for internal SG and PG drivers). This is also best for VCC decoupling, and the

Primary-side current sense resistor’s lower terminal. We can also combine GND an PGND

on to a single large ground plane. Note that Power ground plane is firmly connected to

VPN_OUT, which is the Drain side of the PD’s low-side pass-FET (it stands for Negative Port

Voltage Out).