TMP411CD datasheet(29/61 Pages) TI2

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7.5.6 Timeout Function

When bit 7 of the Consecutive Alert Register is set high, the TMP411/TMP411D timeout function is enabled.

The TMP411/TMP411D device resets the serial interface if the SCL or SDA lines are held low for 30ms (typical)

between a START and STOP condition. If the TMP411/TMP411D device is holding the bus low, the device

releases the bus and waits for a START condition. Maintaining a communication speed of at least 1kHz for the

SCL operating frequency is necessary to avoid activating the timeout function. The default state of the timeout

function is enabled (bit 7 = high).

7.5.7 High-Speed Mode

For the two-wire bus to operate at frequencies above 400kHz, the controller device must issue a high-speed

mode (Hs-mode) controller code (00001XXX) as the first byte after a START condition to switch the bus to

high-speed operation. The TMP411/TMP411D device does not acknowledge this byte, but switches the input

filters on the SDA and SCL lines, switches the output filter on SDA to operate in Hs-mode, which allows transfers

at up to 3.4MHz. After the Hs-mode controller code is issued, the controller transmits a two-wire target address

to initiate a data transfer operation. The bus operates in high-speed mode until a STOP condition occurs on the

bus. The TMP411/TMP411D switches the input and output filter after receiving the STOP condition.

7.5.8 General Call Reset

The TMP411/TMP411D device supports reset through the two-wire general call address 00h (0000 0000b).

The TMP411/TMP411D device reads the general call address and responds to the second byte. If the second

byte is 06h (0000 0110b), the TMP411/TMP411D executes a software reset. The software reset restores the

power-on-reset state to all TMP411/TMP411D registers, aborts any conversion in progress, and clears the

ALERT and THERM pins. The TMP411/TMP411D does not respond to other values in the second byte.

7.5.9 Software Reset

The TMP411/TMP411D resets by writing any value to Pointer Register FCh. This restores the power-on-reset

state to all of the TMP411/TMP411D registers, aborts any conversion in process, and clears the ALERT and

THERM pins.

7.5.10 SMBus Alert Function

The TMP411/TMP411D device supports the SMBus alert function. When pin 6 is configured as an alert output,

the ALERT pin of the TMP411/TMP411D can connect as an SMBus alert signal. When a controller detects an

alert condition on the ALERT line, the controller sends an SMBus alert command (00011001) on the bus. If the

ALERT pin of the TMP411/TMP411D is active, the device acknowledges the SMBus alert command and returns

the target address on the SDA line. The eighth bit of the target address byte indicates if the high limit or low

limit temperature settings caused the alert condition. The bit is high if the temperature is greater than one of the

temperature high limit settings; the bit is low if the temperature is less than or equal to one of the temperature

low limit settings. See Figure 7-8 for details of this sequence.

If multiple devices on the bus respond to the SMBus alert command, arbitration during the target address portion

of the SMBus alert command determines which device clears the alert status. If the TMP411/TMP411D wins the

arbitration, the ALERT pin inactivates when the SMBus alert command is complete. If the TMP411/TMP411D

device loses the arbitration, the ALERT pin remains active.

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TMP411, TMP411D

SBOS383E – DECEMBER 2006 – REVISED JULY 2025

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