AD4084BBCZ datasheet(23/94 Pages) AD

23 / 94 page

Data Sheet

AD4084

THEORY OF OPERATION

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that if VDD11 is not present, the part will be held in a power-on

reset (POR) state, and all AD4084 registers reset to their default

state after the supply has been reestablished. More details on the

POR circuitry can be found in the Power-On Reset (POR) Monitor

section. The VDD33 rail is supplied with an external 3.3V supply.

The VDD33 supply can be removed to further reduce power (see

the Power Saving Operating Modes section), only analog circuity is

held in reset, and the register content remains unaffected. Refer to

Table 1 for the applicable input voltage tolerance for each supply

rail.

As illustrated in the example of Figure 40, external voltage sources

are applied to VDD11 and IOVDD pins.

Figure 40. Externally Sourced Supply Configuration

POWER-ON RESET (POR) MONITOR

The AD4084 power supply monitoring circuits inhibit the converter

functions and reset the configuration memory when supply con-

ditions are outside the specified operating limits. This function

ensures each device is in a deterministic state after power-up.

The power-on function is constructed from two independent voltage

monitors, the first measuring the core 1.1V supply and a second

measuring the voltage at the reference input pin (REFIN). Each

monitor has its own comparator output that is used to decouple the

analog and digital block resets as shown in Figure 41.

Figure 41. Simplified Diagram of POR Circuit

The core VDD (1.1V) supply monitor compares the VDD11 supply

voltage against a preset threshold of 0.93V. If the supply voltage

falls to less than this threshold, a reset signal, POR_D, asserts.

The digital logic reset signal, DIG_RESET, is defined as the logical

combination of the POR_D signal and (logical AND) the compliment

of the SPI software reset function. When either the POR_D signal

(VDD11 < 0.93V) or the SW RESET signal is asserted, the internal

digital circuitry is held in reset. When cleared, the contents of the

configuration registers are restored to the factory default settings.

The reference monitor compares the input voltage at REFIN against

a preset threshold of 2.7V. As illustrated in Figure 41, power for

the reference monitor circuit is supplied from the VDD33 supply.

However, it is important to note that a reference voltage below 2.6V

will cause the part to stop outputting conversion data results. To

recover the conversion process, the reference voltage needs to

be brought to 2.87V. For correct operation of the monitor circuit,

the VDD33 supply must be applied to the AD4084 within the

specified tolerance of 3.3V ± 5% before the reference source is

enabled. Assuming the device is operating within the specified

supply conditions, a reference voltage less than 2.7V results in the

assertion of an internal reset signal, POR_A. The POR_A signal

and (logical AND) the DIG_RESET signal are combined to produce

a reset (ANA_RESET) for the analog circuit blocks including the

ADC core, ADC timer, reference buffer, and so forth. If this reset

signal is asserted, the analog blocks are placed in an inactive state,

and the converter functionality is disabled. This event is indicated

with a value of 1 in the POR_ANA_FLAG bit from the Device

Status Register (Address 0x14). The state of the event detection is

persistent until a Logic 1 is written to the POR_ANA_FLAG bit to

clear the detection state.

POWER SUPPLY SEQUENCE

Table 10 specifies the recommended supply sequences for both

internal and external generation of 1.1V supply rails (IOVDD and

VDD11). Both methods are shown in Figure 42 and Figure 43,

where the supplies that must be provided to the AD4084 are

highlighted in blue, including the REFIN voltage. In both cases,

the AD4084 requires that the supplies are applied in ascending

voltage order. The design must also ensure that voltage is applied

at the analog inputs (IN+ and IN−) and reference input (REFIN)

concurrently with, or immediately following, the VDD33 supply.

Failing in providing REFIN reference voltage on power up will result

in no ADC conversions at the output of the ADC, and continue

to do so until REFIN voltage is provided. Note that test pattern

described in the Data Interface Test Functions section will not

work in the previously mentioned case when a voltage reference

is not provided at the power up. However, if reference voltage was

provided at power up and then removed the test pattern will still

work and output the correct data. As described in the Power-On

Reset (POR) Monitor section, the voltage at the reference input pin

must only be applied once VDD33 is within the specified supply

tolerance to avoid undesired behavior. Therefore, if the selected

voltage reference does not provide an enable pin, it is strongly rec-

ommended to design the reference circuit to power up after VDD33.

After reset or Power-On Reset there is 300us required before part

can be accessed, this is to assure part has all the initialization

procedures done. If this condition is not met, NOT_READY_ERR bit

will be asserted of the INTERFACE_STATUS_A (0x11).

The configuration SPI inputs, CS, SCLK, and SDI, are protected

with clamps to the VDD33 supply rail to allow the inputs to swing

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