UCC28056CDBVT datasheet(41/55 Pages) TI2

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u S u

COMax

Ctrl

Line

Out

u S u

OutMax

Out

Out Re g

Line

Out

4.95 V

)

tan

4.51

)

q u

180

)

tan

u S u

CO1

Out Re g

CO1

Ctrl0

OSRe g

Ctrl0

Out Re g

CO1

u S u

CO1

UCC28056

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SLUSD37E – OCTOBER 2017 – REVISED NOVEMBER 2019

Product Folder Links: UCC28056

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(87)

(88)

Rearranging Equation 86, Equation 87 and Equation 88 yields:

(89)

(90)

(91)

For maximum phase Boost at the gain cross-over frequency, compensator design proceeds by placing the pole

and zero an equal distance above and below the gain cross-over frequency (fB) on the Bode plot. Because the

frequency axis is logarithmic this yields the following pole (fP) and zero (fZ) frequencies:

(92)

(93)

Phase margin of the loop is equal to the phase boost provided by the type 2 compensator, because the

underlying integrator characteristics of the plant and compensator combine to provide 180° of phase lag. To

achieve the desired phase margin (ΦPM) at fB the separation between the pole and zero frequencies may be

found by substituting Equation 92 and Equation 93 into Equation 85, and solving for K in terms of the phase

boost angle.

(94)

The next step is to select the desired phase margin. A typical phase margin range 45° to 75°. For this example

design a target phase margin of 65° is selected.

(95)

(96)

The next step is to determine the loop gain cross-over frequency (fB). A faster loop, results in more twice Line

frequency ripple on the COMP pin voltage, leading to increased Line current distortion.

Begin by setting a target of 1% third harmonic distortion due to twice Line frequency COMP voltage ripple. To

achieve this target, the twice Line frequency COMP pin ripple must be less than 2% of the DC value during

steady-state full power operation. The design proceeds by selecting the loop gain cross-over frequency (fB) that

ensures twice Line frequency COMP pin ripple amplitude does not exceed 2% of its DC level.

Use Equation 97 to calculate twice Line frequency voltage ripple amplitude across the output capacitor.

(97)

The output voltage ripple amplitude must be attenuated by the feedback network to meet our target of 2% ripple

amplitude on the COMP pin voltage.

(98)

Equation 99 simplifies Equation 98.

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