UCC28056CDBVT datasheet(22/55 Pages) TI2

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UCC28056

SLUSD37E – OCTOBER 2017 – REVISED NOVEMBER 2019

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Feature Description (continued)

8.3.5.2.2

Ocp2 Gross Over-Current or CCM Protection

A second comparator (Ocp2) with a higher threshold, and shorter blanking time, also monitors the current sense

voltage signal. If triggered, this second Ocp2 comparator also terminates the current on-time (TON) duration early.

In addition, if the controller triggers the Ocp2 comparator on three consecutive switching cycles, it also triggers a

long fault. The long fault halts switching operation and prevents restart for a period TLongFlt. After this delay, the

controller proceeds with its normal start-up process. In all transient or mild fault conditions the Ocp1 comparator,

with its lower threshold, triggers first and prevents the Ocp2 comparator from acting. The Ocp2 comparator acts

only if there is a gross fault such as a shorted output capacitor or bypass diode.

Under some fault conditions, including output overload, inductor current may become continuous because the

reset voltage is low. In this case even the relatively short Ocp1 blanking time may allow the inductor current to

continue ramping up. The UCC28056 controller addresses this condition by reducing the switching frequency to

allow a longer period for the inductor current to ramp down between on-time pulses.

The maximum allowed diode conduction period (TDCHMax) is doubled in the sequence (250 µs, 500 µs, 1000 µs)

each time the on-time duration terminates early by either one of the OCP comparators. If there is no ZCD signal

to indicate that the inductor current has fallen to zero, then the TDCHMax interval must expire before the next

switching cycle so the switching frequency is halved. The TDCHMax period is halved to reverse the sequence each

time the on-time period does not terminate early by one of the OCP comparators to restore the switching

frequency. If the ZCD signal indicates that inductor current has reached zero, then TDCHMax has no effect and

normal operation resumes automatically.

8.3.5.3 Output Over-Voltage Protection

The UCC28056 controller provides two independent forms of output over-voltage protections. This is done to

ensure that no single fault can result in excessive output voltage.

8.3.5.3.1

First Level Output Over-Voltage Protection (Ovp1)

The VOSNS pin monitors output capacitor voltage via an external resistor divider comprising ROS1 and ROS2. An

internal comparator (Ovp1) monitors the VOSNS pin voltage (VOS). If the voltage on this pin rises above

VOvp1Rise, indicating excessive output capacitor voltage, then the controller transitions to its BstOffb state. In this

state switching halts to prevent further increase in the output capacitor voltage. The controller returns to the Runb

state, and resumes switching operation, only after VOS falls below VOvp1Fall, indicating that the output voltage has

returned to normal range. To limit audible noise, the on-time pulse duration ramps during the transition between

Runb and BstOffb states. This ramp method is identical to that for Burst Mode operation.

8.3.5.3.2

Second Level Over-Voltage Protection (Ovp2)

During the TDCH period when the Boost diode is conducting, (and neglecting impedance in series with the Boost

diode) the voltage across the MOSFET approximates to the output voltage. The controller monitors the voltage

across the MOSFET via an external divider network connected to the ZCD/CS pin. This monitoring provides a

second independent method to detect excessive output voltage in case the VOSNS pin divider becomes

damaged. An Ovp2 comparator with a fixed threshold (VOvp2Th) monitors the ZCD/CS pin voltage during the TDCH

period. A fixed blanking period (TOvp2Blk) is applied after the falling edge of the DRV waveform to ensure that the

Ovp2 comparator is not tripped by inductive spikes on the leading edge of the Drain waveform.

The UCC28056 controller can operate with an in-rush limiting NTC resistor located on the load side of the Boost

MOSFET. Placing the NTC resistor in this location allows the use of a smaller controller with reduced current

rating and delivers better efficiency. The voltage drop across the series resistance introduced by the NTC,

particularly when cold, causes a voltage drop across the Boost MOSFET that is higher than the output voltage,

for example during the early part of the TDCH period when the current flowing through the Boost diode and NTC

resistor is highest. The excess voltage across the Boost MOSFET caused by the a cold NTC has two important

consequences:

•

It may cause the Ovp2 comparator to be tripped when the output voltage is not excessive.

•

Excessive voltage stress applied to the Boost MOSFET, during a cold start, may cause it to be damaged.

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