L99DZ120 datasheet(51/161 Pages) STMICROELECTRONICS

51 / 161 page

DS11567 Rev 5

51/161

L99DZ120

Electrical specifications

160

Note:

See Figure 18: SPI input timing.

Vin_L

Input low level

1.0

Vin_H

Input high level

2.3

Vin_Hyst Input hysteresis

0.2

Ipdin

Pull down current at

input

Vin = 1.5 V

µA

Cin(1)

Input capacitance at

input CSN, CLK, DI and

PWM1,2

Guaranteed by design

fCLK

SPI input frequency at

CLK

4MHz

1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

Table 33. DI, CLK and CSN timing

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

tCLK

Clock period

250

tCLKH

Clock high time

100

tCLKL

Clock low time

100

tset_CSN

CSN setup time, CSN low

before rising edge of CLK

150

tset_CLK

CLK setup time, CLK high

before rising edge of CSN

150

tset_DI

DI setup time

thold_DI

DI hold time

tr_in

Rise time of input signal DI,

CLK, CSN

tf_in

Fall time of input signal DI,

CLK, CSN

Table 32. Inputs: CLK, DI (continued)

Symbol

Parameter

Test condition

Min.

Typ. Max.

Unit

Table 34. Output: DO

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VDOL

Output low level

IDO = -4 mA

0.5

VDOH

Output high level

IDO = 4 mA

V1 - 0.5

IDOLK

3-state leakage

current

VCSN = V1, 0 V < VDO < V1

-10

μA

CDO

3-state input

capacitance

Guaranteed by design

L99DZ120 bảng dữ liệu(PDF) 51 Page - STMicroelectronics

L99DZ120 bảng dữ liệu(HTML) 51 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL