L99LDLH32 datasheet(27/142 Pages) STMICROELECTRONICS

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DS12879 Rev 6

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L99LDLH32

Functional description

141

Where toni is the LED ON-time during step number "i", 1 ≤ i ≤ 255, α ≈ 0.9471, N=254.

For the step number "i" = 0, DC is set to "0".

The function of duty cycle vs 8-bit PWM_DUTY_CHx setting is shown in the following graph.

The minimum duty cycle is clamped to 0.1% in any case.

Figure 7. Duty cycle vs Dimming Step

The duty cycle is configurable through serial bus (PWM_DUTY_CHx, 8 bits per channel –

see RAM memory map, Chapter 7) and the programmed value is stored in the RAM. The

individual duty cycle per channel can be superimposed by a linear 8-bit global dimming

PWM_DUTY_ALL (applicable for outputs mapped to DIN). The resulting duty cycle is the

product of PWM_DUTY_CHx*PWM_DUTY_ALL. Global dimming is not available for

function group not mapped to DIN. If global dimming is not desired, the PWM_DUTY_ALL

Direct Input access to outputs can be enabled or disabled for each channel separately in

Bus / Normal Mode. If Direct Input is enabled (by DIN_EN configuration bit – see RAM

memory map, Chapter 7), bus control is applied when DIN = 0. In case of DIN <> 0, the bus

control is automatically disabled (after tFILTER time) and overtaken by DIN: the DIN input

control has priority versus bus control. After a timeout higher than tBUS_CONTROL after the

last falling edge on DIN, the bus control is reactivated. The characteristics of the function

group is illustrated in the following flow chart.

toni

PWMperiod 

Ni 1

–



–



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