IS25LE512M-RLLA3:P-TY datasheet(148/189 Pages) ISSI

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Giải thích chi tiết về linh kiện	SERIAL FLASH MEMORY 133/112MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

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IS25LE512M

IS25WE512M

Integrated Silicon Solution, Inc.- www.issi.com

148

Rev. A6

06/16/2025

8.50 READ DYB OPERATION (RDDYB, FAh or 4RDDYB, E0h)

FAh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

• FAh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

• E0h is followed by a 4-byte address (A31-A0)

The instruction is used to read Dynamic Protection Bit (DYB) status of the given sector/block. The instruction code

is entered first, followed by the 24-bit or 32-bit address selecting location zero within the desired sector/block as

above. Then the 8-bit DYB access register contents are shifted out. Each bit (SPI) is shifted out at the SCK

frequency by the falling edge of the SCK signal. It is possible to read the same DYB access register continuously

by providing multiples of eight bits. The address of the DYB register does not increment so this is not a means to

read the entire DYB array. Each location must be read with a separate Read DYB instruction.

Note: Data must be either 00h (protected) or FFh (unprotected).

Figure 8.110 Read DYB Sequence In SPI Mode (FAh [EXTADD=0], 3-byte address)

Instruction = FAh

CE #

SCK

...

Mode 3

Mode 0

3-byte Address

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