IS25LE512M-RLLA3:P-TY datasheet(3/189 Pages) ISSI

3 / 189 page

IS25LE512M

IS25WE512M

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A6

06/16/2025

GENERAL DESCRIPTION

The IS25LE512M and IS25WE512M Serial Flash memory offers a versatile storage solution with high flexibility

and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is for systems

that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire

SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable

(CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).

The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies

of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to 66.5Mbytes/s

of data throughput. The IS25xE series of Flash adds support for DTR (Double Transfer Rate) commands that

transfer addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel

Flash memories allowing for efficient memory access to support XIP (execute in place) operation.

Initial state of the memory array is erased (all bits are set to 1) when shipped from the factory.

QPI (Quad Peripheral Interface) supports 2-cycle instruction further reducing instruction times. Pages can be

erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64K/256Kbyte blocks, and/or the entire chip. The uniform

sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad

variety of applications requiring solid data retention.

Automatic ECC Protection (1-bit Error Correction) applies per every 64-bit to maximize reliability.

When ECC is ON, the device allows only single programming operation to each 8-byte ECC boundary between

erase operations.

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