MS85RS1MTY datasheet(16/43 Pages) RAMXEED

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MS85RS1MTY(AEC-Q100 Compliant)

DS501-00096-1v0-E



BLOCK PROTECT

Writing protect block for WRITE command is configured by the value of BP0 and BP1 in the status register.



WRITING PROTECT

Writing operation of the WRITE command and the WRSR command are protected with the value of WEL,

WPEN, WP as shown in the table.



HOLD OPERATION

Hold status is retained without aborting a command if HOLD is “L” level while CS is “L” level. The timing for

starting and ending hold status depends on the SCK to be “H” level or “L” level when a HOLD pin input is

transited to the hold condition as shown in the diagram below. In case the HOLD pin transited to “L” level

when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the same manner, in case

the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H” level at SCK being “H”

level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become do not care.

And, SO becomes High-Z while reading command (RDSR, READ). If CS is rising during hold status, a

command is aborted. In case the command is aborted before its recognition, WEL holds the value before

transition to hold status.

BP1

BP0

Protected Block

None

18000H to 1FFFFH (upper 1/4)

10000H to 1FFFFH (upper 1/2)

00000H to 1FFFFH (all)

WEL

WPEN

Protected Blocks

Unprotected Blocks

Status Register

Protected

Unprotected

Protected

Unprotected

Protected

Unprotected

SCK

Hold Condition

HOLD

Hold Condition

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