SPC563M60X datasheet(63/128 Pages) STMICROELECTRONICS

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SPC563M64x, SPC563M60x

Pinout and signal description

127

3.4

Signal details

Table 6 contains details on the multiplexed signals that appear in Table 4.

Table 5. Pad types

Pad Type

Name

Supply Voltage

Slow

pad_ssr_hv

3.0 V – 5.25 V

Medium

pad_msr_hv

3.0 V – 5.25 V

Fast

pad_fc

3.0 V – 3.6 V

MultiV

pad_multv_hv

3.0 V – 5.25 V (high swing mode)

4.5 V – 5.25 V (low swing mode)

Analog

pad_ae_hv

0.0 – 5.25 V

LVDS

pad_lo_lv

—

Table 6. Signal details

Signal

Module or Function

Description

CLKOUT

Clock Generation

SPC563Mxx clock output for the calibration bus interface

EXTAL

Clock Generation

Input pin for an external crystal oscillator or an external clock

source based on the value driven on the PLLREF pin at reset.

EXTCLK

Clock Generation

External clock input

PLLREF

Clock Generation

PLLREF is used to select whether the oscillator operates in xtal

mode or external reference mode from reset. PLLREF=0

selects external reference mode.

XTAL

Clock Generation

Crystal oscillator input

SCK_B_LVDS–

SCK_B_LVDS+

DSPI

LVDS pair used for DSPI_B TSB mode transmission

SOUT_B_LVDS–

SOUT_B_LVDS+

DSPI

LVDS pair used for DSPI_B TSB mode transmission

SCK_C_LVDS–

SCK_C_LVDS+

DSPI

LVDS pair used for DSPI_C TSB mode transmission

SOUT_C_LVDS–

SOUT_C_LVDS+

DSPI

LVDS pair used for DSPI_C TSB mode transmission

PCS_B[0]

PCS_C[0]

DSPI_B – DSPI_C

Peripheral chip select when device is in master mode—slave

select when used in slave mode

PCS_B[1:5]

PCS_C[1:5]

DSPI_B – DSPI_C

Peripheral chip select when device is in master mode—not

used in slave mode

SCK_B

SCK_C

DSPI_B – DSPI_C

DSPI clock—output when device is in master mode; input when

in slave mode

SIN_B

SIN_C

DSPI_B – DSPI_C

DSPI data in

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