SPSB081 datasheet(50/137 Pages) STMICROELECTRONICS

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Table 22. SPI data length

Bit 6

Bit 5

Bit 4

Description

DL2

DL1

DL0

invalid

16-bit SPI

24-bit SPI

32-bit SPI

…

64-bit SPI

4.3.1.4.1

Data consistency check (Parity/CRC)

Table 23. Data consistency check

Bit 1

Bit 0

Description

Not used

Parity used

CRC used

Invalid

4.3.1.4.2

Watchdog definition

For further information, see also Section 3.6 Configurable window watchdog.

In case a watchdog is implemented the default settings can be read out via the device information registers.

Table 24. WD Type/Timing

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WD1

WD0

WT5

WT4

WT3

WT2

WT1

WT0

Watchdog timeout/Long open window WT[5:0] * 5 ms

OW2

OW1

OW0

CW2

CW1

CW0

Open window OW[2:0] * 5 ms

Closed window CW[2:0] * 5 ms

Invalid

<WD type 1>: 3CH (long open window: 300 ms).

<WD type 2>: 91H (open window. 10 ms, closed window: 5 ms).

<WD type 1> indicates the long open window (timeout) which is opened at the start of the watchdog. The binary

value of WT[5:0] times 5 ms indicates the typical value of the timeout time.

<WD type 2> describes the default timing of the window watchdog.

The binary value of CW[2:0] times 5 ms defines the typical closed window time (tCW) and OW[2:0] times 5 ms

defines the typical open window time (tOW). See figure below where tCW = TEFW and tOW = TLFW - TEFW.

SPSB081

Address definition

DS14048 - Rev 3

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