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L9300 bảng dữ liệu(PDF) 83 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  Automotive flexible U-chip for braking and transmission
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Figure 51. Monodirectional Timing check evolution
Answer
T_Valid_Answ_Start
T_Answ_Timeout
T_Valid_Answ_End
T_start_REQ
T_Answ_Timeout
T_Valid_Answ_Start
T_start_REQ
T_Valid_Answ_End
Request
Answer
GADG0408171055PS
Figure 52. Bidirectional Timing check evolution
Answer
Request
Answer
Request
GADG0408171102PS
T_Answ_TimeOut
T_Valid_Answ_Start
T_start_REQ
T_Valid_Answ_End
T_start_ANSW
T_Valid_Req_Start
T_Valid_Req_End
T_Req_TimeOut
Table 52. Timing parameter legenda
Timing parameter
Description
T_start_REQ
Micro reads, through SPI register seed to elaborated
T_Valid_Answ_Start
Starting time interval for Valid answers
T_Valid_Answ_End
Ending time interval for Valid answers
T_Answ_TimeOut
Time out for answer
T_start_ANSW
Micro sends, through SPI register answer to the ASIC
T_Valid_Req_Start
Starting time interval for next following request
T_Valid_Req_End
Ending time interval for next following request
T_Req_TimeOut
Time out for request
When the Micro finishes its boot procedures, it sends the first Seed request to the device. From this moment all
the timing counters start and cannot be stopped.
The Watchdog Time base is based on the WD frequency of about 250 kHz (clk_4us = SYS_CLK/64). Because of
the resynchronization of the internal signals, the latency between the Answer received and the update of the
WD_Cnt_value is up to 4* clk_4 µs.
The clock used for the timing windows is a divided version of clk_4us in order to obtain a timing resolution of
WD_CLK equal to 64 μs or 256 μs depending on the WD_CLK_DIV settings.
L9300
Q&A Watchdog
DS12258 - Rev 5
page 83/178



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