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MB85RS64T bảng dữ liệu(PDF) 2 Page - RAMXEED LIMITED |
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MB85RS64T bảng dữ liệu(HTML) 2 Page - RAMXEED LIMITED |
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2 / 31 page ![]() MB85RS64T 2 DS501-00058-2v0-E PIN ASSIGNMENT PIN FUNCTIONAL DESCRIPTIONS Pin No. Pin Name Functional description 1 CS Chip Select pin This is an input pin to make chip select. When CS is the “H” level, device is in deselect (standby) status and SO becomes High-Z. Inputs from other pins are ignored at this time. When CS is the “L” level, device is in select (active) status. CS has to be the “L” level before inputting op-code. 3 WP Write Protect pin This is a pin to control writing to a status register. The writing of status register (see “ STATUS REGISTER”) is protected in related with WP and WPEN. See “WRITING PROTECT” for detail. 7 HOLD Hold pin This pin is used to interrupt serial input/output without making chip deselect. When HOLD is the “L” level, hold operation is activated, SO becomes High-Z, and SCK and SI become don’t care. See “HOLD OPERATION” for detail. 6 SCK Serial Clock pin This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. 5 SI Serial Data Input pin This is an input pin of serial data. This inputs op-code, address, and writing data. 2 SO Serial Data Output pin This is an output pin of serial data. Reading data of FeRAM memory cell array and status register are output. This is High-Z during standby. 8 VDD Supply Voltage pin 4 VSS Ground pin DIE PAD It is allowed for the DIE PAD on the bottom of the SON8 package to be floating (no con- nection to anything) or to be connected to VSS. VSS SI SO VDD SCK WP CS HOLD 8 7 6 5 4 3 2 1 (TOP VIEW) (FPT-8P-M02) |
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