MB85RS64T

6

DS501-00058-2v0-E



STATUS REGISTER



OP-CODE

MB85RS64T accepts 8 kinds of command specified in op-code. Op-code is a code composed of 8 bits shown

in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code,

the command are not performed.

*

1:When this command is input, SO output will be unvalued.

Bit No.

Bit Name

Function

7

WPEN

Status Register Write Protect

This is a bit composed of nonvolatile memories (FeRAM). WPEN protects

writing to a status register (see “ WRITING PROTECT”) relating with WP

input. Writing with the WRSR command and reading with the RDSR com-

mand are possible.

6 to 4



Not Used Bits

These are bits composed of nonvolatile memories, writing with the WRSR

command is possible, and “000” is written before shipment. These bits are

not used but they are read with the RDSR command.

3

BP1

Block Protect

This is a bit composed of nonvolatile memory. This defines size of write

protect block for the WRITE command (see “ BLOCK PROTECT”).

Writing with the WRSR command and reading with the RDSR command

are possible.

2

BP0

1

WEL

Write Enable Latch

This indicates FeRAM Array and status register are writable. The WREN

command is for setting, and the WRDI command is for resetting. With the

RDSR command, reading is possible but writing is not possible with the

WRSR command. WEL is reset after the following operations.

After power ON.

After WRDI command recognition.

0

0

This is a bit fixed to “0”.

Name

Description

Op-code

WREN

Set Write Enable Latch

0000 0110B

WRDI

Reset Write Enable Latch

0000 0100B

RDSR

Read Status Register

0000 0101B

WRSR

Write Status Register

0000 0001B

READ

Read Memory Code

0000 0011B

WRITE

Write Memory Code

0000 0010B

RDID

Read Device ID

1001 1111B

SLEEP

Sleep Mode

1011 1001B

RFU

Reserved for future use*1

0000 1011B