STA333BW datasheet(24/68 Pages) STMICROELECTRONICS

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STA333BW

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The relationship between the input clock and the input sample rate is determined by both

the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor

generating the internal clock and the IR bit determines the oversampling ratio used

internally.

Interpolation ratio select

The STA333BW has variable interpolation (oversampling) settings such that internal

processing and FFX output rates remain consistent. The first processing block interpolates

by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The

oversampling ratio of this interpolation is determined by the IR bits.

Table 11. Input sampling rates

Input sample rate

fs (kHz)

MCS[2:0]

101

100

011

010

001

000

32, 44.1, 48

576 * fs

128 * fs

256 * fs

384 * fs

512 * fs

768 * fs

88.2, 96

64 * fs

128 * fs

192 * fs

256 * fs

384 * fs

176.4, 192

32 * fs

64 * fs

96 * fs

128 * fs

192 * fs

Table 12. Internal interpolation ratio

Bit

R/W

RST

Name

Description

4:3

R/W

IR [1:0]

Selects internal interpolation ratio based on input I²S

sample frequency

Table 13. IR bit settings as a function of input sample rate

Input sample rate fs (kHz)

1st stage interpolation ratio

2-times oversampling

44.1

2-times oversampling

88.2

Pass-through

176.4

2-times downsampling

192

2-times downsampling

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