DAC7568IAPWR.A datasheet(39/72 Pages) TI2

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DAC7568, DAC8168, DAC8568

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SBAS430F – JANUARY 2009 – REVISED APRIL 2018

Product Folder Links: DAC7568 DAC8168 DAC8568

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8.2.7

SYNC Interrupt

In a normal write sequence, the SYNC line stays low for at least 32 falling edges of SCLK and the addressed

DAC register updates on the 32nd falling edge. However, if SYNC is brought high before the 31st falling edge, it

acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither

an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (as

shown in Figure 123).

8.2.8 Power-on Reset to Zero Scale or Midscale

The DAC7568, DAC8168, and DAC8568 contain a power-on reset circuit that controls the output voltage during

power-up. For device grades A and C on power-up, all DAC registers are filled with zeros and the output

voltages of all DAC channels are set to zero scale. For device grades B and D all DAC registers are set to have

all DAC channels power up in midscale. All DAC channels remain that way until a valid write sequence and load

command are made to the respective DAC channel. The power-on reset is useful in applications where it is

important to know the state of the output of each DAC while the device is in the process of powering up. No

device pin should be brought high before power is applied to the device. The internal reference is powered off /

down by default and remains that way until a valid reference-change command is executed.

8.2.9 Clear Code Register and CLR Pin

The DAC7568, DAC8168, and DAC8568 contain a clear code register. The clear code register can be accessed

via the serial peripheral interface (SPI) and is user-configurable. Bringing the CLR pin low clears the content of

all DAC registers and all DAC buffers, and replaces the code with the code determined by the clear code

must be set as follows to access the clear code register that is programmed via the feature bits, F0 and F1: C3 =

'0', C2 = '1', C1 = '0', and C0 = '1'. The default setting of the clear code register sets the output of all DAC

channels to 0V when CLR pin is brought low. The CLR pin is falling-edge triggered; therefore, the device exits

clear code mode on the 32nd falling edge of the next write sequence. If CLR pin is brought low during a write

sequence, this write sequence is aborted and the DAC registers and DAC buffers are cleared as described

previously.

When performing a software reset of the device, the clear code register is set back to its default mode (DB1 =

DB0 = '0'). Setting the clear code register to DB1 = DB0 = '1' ignores any activity on the external CLR pin.

8.2.10 Software Reset Function

The DAC7568, DAC8168, and DAC8568 contain a software reset feature. If the software reset feature is

executed, all registers inside the device are reset to default settings; that is, all DAC channels are reset to the

power-on reset code (power on reset to zero scale for grades A and C; power on reset to midscale for grades B

and D).

Table 5. Clear Code Register

DB30-

DB28

DB19-

DB10

DESCRIPTION

Don't

Care

D16-

GENERAL DATA FORMAT

Clear all DAC outputs to zero scale (default

mode)

Clear all DAC outputs to midscale

Clear all DAC outputs to full-scale

Ignore external CLR pin

Table 6. Software Reset

DB30-

DB28

DB19-

DB10

DESCRIPTION

Don't

Care

D16-

GENERAL DATA FORMAT

Software reset

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