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STAMP0 bảng dữ liệu(PDF) 31 Page - STMicroelectronics

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STAMP0 bảng dữ liệu(HTML) 31 Page - STMicroelectronics

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STAMP0
Architecture
DocID028639 Rev 1
31/62
Table 9: Sync clock frequencies
Reg.0x07
(hex value)
SYNC_CLK_N
(decimal value)
SYNC_CLK (Fs = 44.1 kHz)
(MHz)
SYNC_CLK (Fs = 44.1 kHz)
(MHz)
0x68
40
2.25792
2.4576
0x6A
42
2.1504
2.340571
0x6C
44
2.052655
2,234182
0x6E
46
1.963409
2.137043
0x70
48
1.881600
2.048000
0x72
50
1.806336
1.966080
0x74
52
1.736862
1.890462
0x76
54
1.672533
1.820444
0x78
56
1.6128
1.755429
0x7A
58
1.55718
1.694897
By default SYNC_CLK output is low when the chip powers up and stays low until the I²C
SYNC_CLK_EN is not set to one. Moreover the SYNC_CLK output stays low when PLL is
not locked. Finally when PLL changes from locked to unlocked, the SYNC_CLK output
changes to low and an interrupt is generated.
4.8.7
MIC clock out generator
This block receives as input SYS_CLK and it generates a PDM_MIC_CLK clock signal
whose frequency is equal to 64xFs.
By default the PDM_MIC_CLK output is active and can be disabled by setting the I²C
register (Reg. 0x08 bit B4) to zero.
4.8.8
PLL and oscillator power-down
In the STAMP0 device it is possible to power off/on both the oscillator and the PLL using
the I²C register (Reg. 0x2D bit B0).
Obsolete
Product(s)
- Obsolete
Product(s)



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