STAMP0 datasheet(30/62 Pages) STMICROELECTRONICS

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Architecture

STAMP0

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DocID028639 Rev 1

Table 8: PLL frequency values

SCKxFs

SCK frequency (Fs = 44.1 kHz / 48.0 kHz)

IDF

NDIV

PLL_CLK

64 Fs

2.8224 MHz / 3.072 MHz

90.3168 MHz /98.304 MHz

128 Fs

5.6448 MHz / 6.144 MHz

90.3168 MHz /98.304 MHz

256 Fs

11.2896 MHz / 12.288 MHz

90.3168 MHz /98.304 MHz

4.8.2

Oscillator

The STAMPO internal oscillator guarantees the functionalities of all the internal blocks

either if the PLL is unlocked or a low clock is detected. Its output frequency is equal to 20

MHz.

4.8.3

PLL autoconf

The PLL AutoConf main functionalities are:

•

PLL programming either using the I²C registers Reg. 0x01 and 0x02 (PLL manual

programming mode), or the SCK and FSY TDM external signals (automatic

programming mode). The automatic and the manual PLL programming functionalities

work only if both the SCK and FSY external clocks are given.

•

SCK and FSY frequencies integrity monitoring (both in manual and in automatic

programming mode)

•

SCK_RATE frequency computation (only in manual mode)

This block receives as input the SCK, FSY, I²C_AUTOPLL, I²C_IDF and the I²C_NIDV

signals and it generates the IDF and NDIV signals required to program the PLL, and the

SCK_rate value to configure the channel mapping and the TDM interface.

This block generates an interrupt as soon as the FSY/SCK ratio differs from 64, 128 and

256.

4.8.4

Low-clock check

This block is a simply an SCK low frequency detection circuit. In particular it receives as

input the SCK clock signal, the oscillator output frequency, and it generates the output

LOWCKS signal equal to ‘1’ as soon as the SCK clock frequency falls below an internal

threshold. The output of this block can be monitored using the I²C register (Reg. 0x06, bit

B0).

4.8.5

PLL_OSC_SEL

This block receives as input the LOWCKS, PLL_LOCK and the I²C_PLLBYP (Reg. 0x05,

bit B2), and it generates as output the BYPASS_INT signal. The BYPASS_INT signal is

equal to ‘1’ either if the PLL is unlocked or the LOWCKS signal is set to ‘1’. In all the other

cases the BYPASS_INT signal is equal to ‘0’. Moreover the PLL can be bypassed through

the I²C register REG 0x05 Bit 2 (I²C_PLLBYP signal in Figure 21: "Clock manager

architecture").

4.8.6

SYNC clock generator

This block simply receives as inputs the SYS_CLK, the I²C SYNC_CLK_N signal (Reg.

0x07 bits B5, B4, B3, B2, B1, B0), the I²C SYNC_CLK_EN signal (Reg. 0x07, bit B6) and it

generates the SYNC_CLK frequency according to the value given in Table 9: "Sync clock

frequencies".

Obsolete

Product(s)

- Obsolete

Product(s)

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